Recent content by devuniv

What is "CPU execution ports"? Like ones spoken about here (somewhere in the middle): https://www.gamedev.net/articles/programming/general-and-gameplay-programming/a-journey-through-the-cpu-pipeline-r3115/

I thought certain CPU core makes one inquiry (asks to fetch cache line number n) to L1 cache (or to L1 TLB) and waits for the result. L1 cache is dedicated to a single core. So it seems nonsense to make 8 such inquiries in parallel. So why "8 lines"? What are these "8 lines" for?

From wikipedia "memory bus is the computer bus which connects the main memory to the memory controller". But how exactly datastream travels from DRAM memory chip into CPU and back? Where is the place when data from "outside" main memory get into CPU (its L3 cache)? I don't think data flows...

Who can change main memory contents besides CPU itself? Wikipedia speaking about working of CPU caches that "data in the main memory may be changed by other entities than CPU itself (e.g. peripherals using direct memory access (DMA)". Could you give a real-life use-case / example of this...

Modern processors (especially Intel) integrated graphics has its own cache(s) or it uses shared L3 cache of "regular" CPU cores? Integrated graphics core(s) have their own separate L1, L2, L3 caches (instruction and data caches) and their own separate TLB just like regular CPU and its regular...

Do modern GPUs (graphics core) built-in in CPU use CPU cores or it is just another (additional) core for graphics? Or integrated graphics does some calculations itself and asks CPU cores to do some encoding work, etc? So if I have Intel i7 CPU with 4 cores, do I really have, say, 5 cores -...