Recent content by Fe4rlessCloak

Most of these can be resolved through proper scheduling, which is easier said than done since we haven't achieved a proper solution, yet. The Skymont LPE-core cluster on LNL measures 6.89mm^2 (N3B), compared to 5.90mm^2 on MTL (Intel 4). Not really apples to apples, since we're comparing LPE to...

This entire story was sourced from a 'leaked' memo. Your current headline makes it sound like a matter of fact, which it isn't. Tom's Hardware, like other sites, probably has editors pushing for view-grabbing headlines, but a leak or tip should require more careful wording. It puts you in the...

(8P + 16E) * 2 + 4 LPE = 52 Cores

It's simple. AMD's CCDs are not dependent on the cache chiplet since they have their own cache ( L1 + L2 + L3 ). The additional chiplet simply extends the existing L3 cache. In Intel's approach, they're mutually dependent ( one can't exist without the other ) but in AMD, they aren't ( one can...

Wish they'd drop the 7800X3D's price now :/

While they're intended for the same modes (Balanced / Quality / Ultra Quality), the old ones are outdated, or at least the newer versions ( E and F) are better from what I remember.

Probably 288 or so. I believe 4 CPU tiles have 96 cores ( saw this on WCCFTech a while back )... Or 24 per each CPU tile... Since there are 12 CPU tiles: 12*24 = 288 but that's just a guess.

They're trying to say that the CPU Tile and Base Tile ( cache ) exist as a complete package and hence are dependent on one another ( mutually dependent ). You can't have CPU cores without cache and vice versa.