Recent content by SiliconFly

Welcome to the new Tom's Hardware!

I don't think any respected tech sites are dumb enough to dilute their reputation with these kinda of brainless click baits. Hurts their bottom line in the long run. Looks more like an oversight that they've allowed one of their intern/new/junior reviewer to post this foolish article without...

This is probably the most stupidest tech article I've come across in recent times. A Tom's Hardware reviewer who's comparing GPUs doesn't even know he has to test it with same/similar resolutions, otherwise the GPU will grossly under perform. He's comparing Intel GPU with a resolution of...

Well, considering Intel's current execution with Intel 7 & Intel 4, I think they're going to do a better job with 20A too! Just that this radio silence is too eerie!

Any news on the health of Intel 20A? Will it enter volume production in Q2 2024 as planned? Some rumors suggest that might not be the case. Or is it just some fanboy FUD?

Seems L4 is ultra power efficient and doesn't need to be powered down. Instead, in the new low-power state, when the frame buffer doesn't need to be updated, the video memory can be buffered in the cache while idling and the tGPU can be powered-off as well.

Also, a while ago, that idiot MLID suggested that the ADM L4 will be separate tile between the base tile and the substrate. And i was scratching my head why on earth Intel would do something stupid like this for no apparent advantage. After digging deeper, it's now clear that the ADM L4 is part...

Came across a new rumor. Note: It's just a rumor/speculation based on an assumption. Even though a leaked Intel slide suggested that ADM L4 will be paired with tGPU, I recently came across a detailed analysis that seems to suggest that ADM L4 might not be paired directly with the tGPU, but with...

There's been a slew of ES leaks recently regarding MTL-P. This is the latest B0 stepping. It shows the base clock as 3.1 GHz and the CPU idiling at 640 MHz!! Very impressive! Is it the base clock of the E-core? Or one of the new ULP E-cores?

Ok. Will start sharing some interesting stuff and try to get things active again.

Well, I did i sense some sort of discomfort in this thread for reasons beyong me. Recommend one of the senior members to start a new open thread specifically for Intel discussions. Would make life easier for many.

Looks like this thread has gone inactive. Is it okay to post here?

This was leaked a long while ago. And at that time, many didn't notice. It all makes sense now! If we read it carefully, it clearly says ADM is paired with GT2P!!! Thats the tGPU in MTL-P Also says with LNC, ADM is paired with GT3. Thats cool! :blush:

Actually, by nature, ADM L4 adds significant latency. This latency becomes a huge issue when cache misses exceeds cache hits. So, when the cache hits are low, the significantly increased DRAM access time will seriously degrade tCPU performance. ADM working as L4 seems very unlikely. Or do they...

Very true. ADM acting as a L4 cache will introduce too steep a penalty. Looks like it's destined for the tGPU primarily.