Recent content by ToBeGood

Intel Product "alone" is going to save Intel Foundry. Do you know that Apple is like 40% of all TSMC revenue in 2022. Do you know how many things that intel is FABing / making. 80% of Laptop CPU. 50% of Server CPU. All the chipset mentioned above In 2025, I am estimating that Arc Battlemage...

According to Intel Financial Report, Intel still yet received 1c from the CHIPS act as of Q2 2024. <Mod Edit - delete off topic political>

One thing that I really don't understand is that if that is really the case, why Intel can't product, accept the loss and move on? The loss (increase of) of 10%-20% COGS for the next 6 months and 10%-15% (for next 12 months) is totally acceptable (or Not?)? Even there is no density improvement...

Please can I have the same data from TSMC, the ratio and rational is all come from TSMC PowerPoint, the fanboy out there living in its world always used Xnm+++++ to intel, even long after Intel 20A naming, we are not crying babies, I just want to say, the same has to happen, There is no TSMC A16...

Hi TSMC Fanboys @The Historical Fidelity @NinoPino Regardless these are fact, intel prepared (a possible biased) paper vs TSMC ~x% which one I need to say, there are a lot of professional website out there that mentioned that TSMC N3E = N5 SRAM in um2 i.e. 0.021um2 (HDC) and 0.025um2 (HCC)...

Although it is just only a powerpoint at this moment, but the paper on PPA the graph just plot Intel 3 @ 0.65V can clock to Apple M4 i.e. 4.4 GHz, meaning that we should see Xeon 6 (Rapid one), should clock at this speed. So What Intel indirectly saying is that Intel 3 can clock at least the...

Hi TSMC fanboy, Sssssh, just want to say to you quietly that N3E is N5++ is a 5nm class device, N3B != N3E Sssssh, Intel Sierra Forest is now out as well, just same time frame is Apple M4, Sssssh, Intel catch up with TSMC. Sssssh, do let the TSMC shareholder knows.

No one knows what is discussed. Half glass full vs Half glass empty. The same report can also line it this way and it make perfect sense. Apple COO goes to visit CC Wei @ TSMC to discuss whether they are still going to manufacture all their product with TSMC. (Half Glass Empty) You needed to...

What are you talking about ???? https://semiengineering.com/fillcut-self-aligned-double-patterning/ "while SADP generates the pitch (mask) split using spacers that are self-aligned to the first litho-etch step. The second mask in an SADP process is a block or cut mask used to trim the tips of...

Sound totally non-sense. The real reason why TSMC fire its Chair is not because of US FAB, this delay is the No1 reason why he is sacked. https://www.cnbc.com/2022/03/23/inside-asml-the-company-advanced-chipmakers-use-for-euv-lithography.html If TSMC N3B can have good yield and not leading to...

Dear Anton Shilov, Please don't change your heading because there are analyst out there want to limited it's lost. https://investor.tsmc.com/chinese/encrypt/files/encrypt_file/reports/2023-10/b2fc08165bbaf6fc1a2db26500e6f78f1db85ebd/TSMC%203Q23%20Transcript.pdf C. C. Wei - Taiwan Semiconductor...

I think I interrupted the translation different than what is in English. "... it does not pose a substantial threat to TSMC unless it manages to enhance various facets of its foundry operations like technological leadership, yield rates, and competitive pricing. Meanwhile, even if Intel...

1nm 0.x nm is just a marketing slogan, Just give you a food for through silicon atom is 0.2 nm so you think a transistor can be anywhere 9 atoms wide (it just very difficult.

Yes we do have some estimate data for you sake. Intel 4 Backside Power Delivery is 95% Cell Utilization Rate. "The density of these cells is also quite impressive. By moving to backside power delivery, Intel was able to utilize 95% of the space within one of the denser spots within the E-core...