News 10nm Ice Lake CPU Meets M.2: The 'Spring Hill' Nervana NPP-I Deep Dive

So we are looking at the high end version of a Math Co-Processor.

Runs back to my old 486 SX 33. "I knew saving you was for the good of us all!"
Yep, sounds like it, but just for a different purpose. Everything comes around just like we all used mainframes etc with terminals on our desks to stand alone computers now back to basically mainframes in a sense with the cloud. Lifes just one big circle. :)
 
So we are looking at the high end version of a Math Co-Processor.

Runs back to my old 486 SX 33. "I knew saving you was for the good of us all!"
The old 80486SX models do not have a math co-processor. Only the 80486DX models have them.
 
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So, looks like the intent is that the processing is done by the Cadence Tensilica V6 DSPs , one per ICE. The two sunny cove processors add two avx512 units, including dlboost, but also fp32 operations, which wouldn't be the primary processing.

I noticed the Hololens 2 also uses these DSPs

You can get clear pdfs of the slides through the intel newsroom announcement.
 
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The old 80486SX models do not have a math co-processor. Only the 80486DX models have them.

Sorry I didn't reply to this sooner. I know the SX version didn't have a math co-processor. I remember the choice and the price difference when I got my machine back then. I didn't need the extra power so I went cheap. Oh yeah I could run DOS 6.2 with Windows 3.1 great on that baby.
 
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Sorry I didn't reply to this sooner. I know the SX version didn't have a math co-processor. I remember the choice and the price difference when I got my machine back then. I didn't need the extra power so I went cheap. Oh yeah I could run DOS 6.2 with Windows 3.1 great on that baby.
And if the motherboard features a socketed CPU then can upgrade to 80486DX or 80486DX2. The math co-processor can often have significant performance difference in 3D games and some software. However if the motherboard features a soldered QFP CPU then no upgrade path. Also sometimes those motherboards have a socket for the math co-processor, but getting one of those math co-processors is rather difficult.
 
So, looks like the intent is that the processing is done by the Cadence Tensilica V6 DSPs , one per ICE.

To reply to my own comment ... after reading more, it looks like those Tensilica DSPs have a minor role relative to the processing that occurs in those big multiplier arrays.
 
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