[SOLVED] 2x rxt3090 and 2x8 lanes?

tclancey

Honorable
Jun 6, 2015
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How does 2x 8 and 1x 16 work out?

It's been over 20 years since I built a pc from individual parts and things have moved on a bit. I have most of it worked out in my head, but the 2x8 vs 1x16 on the pice slots has me a little confused and concerned.

For modelling and rendering support (mostly blender) I want a 2x RTX 3090 setup, I have a good z690 Rog Maximus board, 12900k, power supply, m2 drives, 5600 memory etc so the system as a whole will be fine, I'm very much looking forward to the rendering speed of this setup.

However, I also have to test the models created in Blender in real time games, and I enjoy spending a few hours sim racing a week. These activities will only utilise one card, splitting the 16 lanes available for the 2 cards means each running on only 8 lanes, is this going to impact performance much? Will the 12900 and bios be able to take the throughput without any bottle necks?

I don't want to be hitting the bios every time I want to switch activities.

Many thanks.
 
Solution
Those lanes are interfacing periphery (add-on cards) to the CPU.
More lanes provide more traffic throughput.
For heavy calculations (mining is a good example) the data is loaded and worked on in the card memory, so one set of lanes is sufficient to provide full performance in most cases.
For real-time applications, with large amounts of data but simple calculations, the throughput may become a bottleneck. Data is not worked on until loaded.
Those lanes are usually steerable (routed) which is controlled using the chipset.
Simply put, the heavier the calculations are, the less data movement is required and less benefit from higher bandwidth (16 lanes) is achieved.
With PCiE 4, 8 sets of lanes provide as much throughput as 16 sets of...
Those lanes are interfacing periphery (add-on cards) to the CPU.
More lanes provide more traffic throughput.
For heavy calculations (mining is a good example) the data is loaded and worked on in the card memory, so one set of lanes is sufficient to provide full performance in most cases.
For real-time applications, with large amounts of data but simple calculations, the throughput may become a bottleneck. Data is not worked on until loaded.
Those lanes are usually steerable (routed) which is controlled using the chipset.
Simply put, the heavier the calculations are, the less data movement is required and less benefit from higher bandwidth (16 lanes) is achieved.
With PCiE 4, 8 sets of lanes provide as much throughput as 16 sets of gen3, which is still quick. The real bottleneck is the data calculation speed of those cards, as long as the rendering software will be able to utilize both at the same time.
 
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