400MHz FSB is not *that* great

[Guest]

I've heard too much stuff about how good the P4's quad-pumped 400MHz FSB is. Well, the Pentium III has a 133MHz bus, and until recently, the Athlon had a 200MHz bus.

133MHz x 1.5 = 200MHz

Most people agree that the PIII can more-or-less equal the Athlon (SDR, 200MHz FSB) at the same clock speed overall. The new Athlons have 266MHz FSB:

266MHz x 1.5 = 400MHz

So, surely the Athlon (DDR, 266MHz) should be able to compete with the P4, it's the same factor. 400MHz just sounds bigger because it has a four in front. I've heard rumors anyway that Palamino or Mustang will have a 2x150MHz = 300MHz FSB, which ain't far off.

 

[Grizely1]

Few things, although I agree for the most part:

The new Athlons have 266MHz FSB:

266MHz x 1.5 = 400MHz

It doesn't work this way. It's not 266MHz x 1.5, it's 133x1.5 because the 266MHz FSB is just double pumped, similar to p4's "quad pumped" FSB.

Also the Mustang was dropped from the list of stuff coming from AMD, so it's just the Palomino in the next bit, and the Palomino will also have 266MHz.

 

[Zenthar]

AMD 200Mhz bus = 100Mhz X 2
AMD 266Mhz bus = 133Mhz X 2

Intel 400Mhz bus = 100Mhz X 4

Basicaly they just find a way to send data more than one time per cycle. Still it would be interesting to compare a pure 200Mhz bus vs a 100Mhz X 2.

 

[FUGGER]

Zenthar is correct, AMD started the "double pumped" FSB. Funny how some of you didn't even know that fact.
P4 has superior bandwidth compared to current athlon machines.

You can overclock the FSB of the P4, the 100Mhz FSB is only first logical step in ramping up.

 

[Guest]

Actually, AMD's double pumped EV6 bus was licensed from Compaq. The bus was originally designed and used on the DEC Alpha so AMD did not start it. EV6 is capable of 400MHz and, if I'm not mistaken, the new EV8 can do 800MHz.

 

[jg38141]

True- Ev6 started the whole shabang in 1997 I think, correct me if I'm wrong on this.

"Are you saying that I can dodge bullets?"

 

[Guest]

I know about quad-pumping and double-pumping. It doesn't really matter though. You get the same throughput in gigabits per sec whether you have a "pure" 200MHz bus or a 100MHz bus double-pumped. Same with the P4. They could have used a "pure" 400MHz bus but the 100x4 has the same throughput.

Busses work using a sine wave. Traditionally, data has only been sent on the rising edge of the clock pulse. With DDR and the EV6 bus, it is sent on the rising and falling edges, doubling the throughput.

I believe the P4 quad-pumped bus works in a slightly different way, although how it works exactly, I don't know. The point is this: it's hard to make a "pure" bus this fast which can get all the way from the chip to the Northbridge, it's easier via this slight of hand that Compaq/Intel/AMD are now using.

You can say 266MHz x 1.5, because the "perceived" speed of the bus is 266MHz, and the "perceived" speed of the P4 bus is 400MHz, no matter whats going on under the hood. It's like a V8 engine - you have twice the cylinders, but the effect is that the car just goes faster, you don't have to understand what's happening underneath.

The only way a double-pumped or quad-pumped bus could be slower than a pure bus at that speed is if the actual DDR/QDR process requires some overhead on the chipset's part. I doubt it can account for much, though.

Incidently, Grizley1, how to you do those cool 'in reply to' thingies? Tell me or I'll beat you with a crowbar when I go to Canada in Feb

 

[Grizely1]

Oh, those are easy! Just highlight want to want to put in the "in reply to" thingy and copy it. Then when you're replying, just put [ quote ] (without the spaces in between brackets) and then paste the text you want in the in reply to thingy, then after the text type [ /quote ] (without the spaces again of course)

like this:

hi this is a test

 

[Guest]

Since all viewers here are well versed in what Tom has to say, then we all are aware of the performance deficiencies in the PIV. Why does it lag?...Why don't you ask the software manufacturers? I can't go into the specifics, but picture it much like the SMP (Symetrical Multi-Processor) scenario. The processor has the ability to Quad Pump, when, and only when, it's instructed to do so. Hmmm...