Thanks to some new <A HREF="http://www.tomshardware.com/technews/index.html" target="_new">R&D advancements</A>, it looks like we will be seeing some massive bandwidth in just a couple years' time. I will put forth a technical explanation below.
Current forms of RDRAM are a DDR (Double Data Rate) technology. For whatever memory clock is used, they transmit twice per clock. The i850 chipset provides a 400MHz memory clock (FSB). The RDRAM modules transmit twice per clock for an effective 800MHz rate. This provides 1.6GB/s of memory bandwidth per 16-bit channel. The i850 chipset provides two of these channels to obtain the advertised 3.2GB/s of memory bandwidth.
A new <A HREF="http://www.tomshardware.com/technews/index.html" target="_new">Octal Data Rate</A> (ODR) technology has been developed that can transmit 8 times per clock. If you kept the same 400MHz FSB clock, then this would be an effective 3200MHz (3.2GHz) rate. Note that this is still on a per-16bit-channel basis. This provides 6.4GB/s of memory bandwidth per 16-bit channel. On a dual-channel chipset with a 400MHz FSB this would provide 12.8GB/s of memory bandwidth.
Now this might not sound very impressive yet. After all, this is over 2 years away. We should get more than 4 times current bandwidth with 2 years of research and development. This is where the fun starts. 16-bit RDRAM channels will be a thing of the past in the second half of 2002. We will be using 32-bit channels by then, and 64-bit channels by 2004. In addition to this, by the second half of 2002 RDRAM platforms will be using a 533MHz FSB clock (PC1066). By 2004 they will be using a 600MHz FSB clock (PC1200).
Couple the ODR technology with dual 64-bit channels running off a 600MHZ FSB clock and you get 76.8GB/s of memory bandwidth. 76.8GB/s of memory bandwidth in just over 2 years is pretty nice, is it not?
-Raystonn
= The views stated herein are my personal views, and not necessarily the views of my employer. =
Current forms of RDRAM are a DDR (Double Data Rate) technology. For whatever memory clock is used, they transmit twice per clock. The i850 chipset provides a 400MHz memory clock (FSB). The RDRAM modules transmit twice per clock for an effective 800MHz rate. This provides 1.6GB/s of memory bandwidth per 16-bit channel. The i850 chipset provides two of these channels to obtain the advertised 3.2GB/s of memory bandwidth.
A new <A HREF="http://www.tomshardware.com/technews/index.html" target="_new">Octal Data Rate</A> (ODR) technology has been developed that can transmit 8 times per clock. If you kept the same 400MHz FSB clock, then this would be an effective 3200MHz (3.2GHz) rate. Note that this is still on a per-16bit-channel basis. This provides 6.4GB/s of memory bandwidth per 16-bit channel. On a dual-channel chipset with a 400MHz FSB this would provide 12.8GB/s of memory bandwidth.
Now this might not sound very impressive yet. After all, this is over 2 years away. We should get more than 4 times current bandwidth with 2 years of research and development. This is where the fun starts. 16-bit RDRAM channels will be a thing of the past in the second half of 2002. We will be using 32-bit channels by then, and 64-bit channels by 2004. In addition to this, by the second half of 2002 RDRAM platforms will be using a 533MHz FSB clock (PC1066). By 2004 they will be using a 600MHz FSB clock (PC1200).
Couple the ODR technology with dual 64-bit channels running off a 600MHZ FSB clock and you get 76.8GB/s of memory bandwidth. 76.8GB/s of memory bandwidth in just over 2 years is pretty nice, is it not?
-Raystonn
= The views stated herein are my personal views, and not necessarily the views of my employer. =