76.8GB/s of memory bandwidth in 2004

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Matisaro

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Hmmmmm, I dont know which set of big words to believe.


Salvo, you sound rather educated, I should warn you raystonn is very respected on the forum, even if you are right. (personally I agree that the hige figure is reaching) the backlash of those which will side with raystonn out of respect is not worth the small victory being right would bring. I say rayya dn salvo should just agree to disagree and let it go, anyone agree?

~Matisaro~
"The Cash Left In My Pocket,The BEST Benchmark"
~Tbird1.3@1.5~
 

LoveGuRu

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hay man you know i love you too but this is not a prom queen contast, "respect" is really irelevent here.
we are(i admit that i am anyway)ignorant in this micro architechture stuff(almost wrote BS:p), this is not my terretory of buseness, althogh its very intresting, its been a long while since i learned to write asembly language, so allot of things changed, if some one stated what we consider as "facts" and does not mention any other alternative, we might just accept it but at other occasion when some one would ask us we will asnwer just that.

so respect or not another opinion is very important, specially at delecate subjects such as these.

-sorry for the MANNY(!!) mistakes, im not nate english speaker.

<font color=green>
*******
*K.I.S.S*
*(k)eep (I)t (S)imple (S)tupid*
*******
</font color=green>
 
G

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"Operating at 2.4 GHz is major league stuff, where 133 MHz (some 20 times less) is minor league. "

Hardly, major league. Your right that, since this is really the first time when this type of analysis has been necessary for developing commercial PC type circuit board equipment, the majority of existing PCB designers, and engineers are ill equiped to deal with it. This stuff has really been around for years, it's all well described and, documented for anybody who cares enough to do the necessary research, and sweat into learning what is up. There are plenty of circuit designers in existence who deal with this stuff every day, and for whom it would be second nature to do this type of work.

Why do you keep picking on the poor dude? He already admitted he does some type of software work and testing. He never said anything about high speed circuit board layout. Besides I never got the impression that Raystonn had said this will definitely show up in PC hardware, but rather he was just pointing some interesting new technology and offering a few opinions about what it might be good for.

If your trying to debunk the whole idea with the argument that some connector is crappy, and would cause the whole idea to not work then I think you don't have much of an argument. Even if this technology doesn't take off, I rather doubt it will be because no one can do a decent high speed circuit board design.
 

Raystonn

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"As they say, you can lead a mule to the water hole but..."

That is 'horse'. I do not appreciate the trollish comments.


"there’s a huge difference between operating a bus at 133 MHz (PC2100) and operating one at 2.4 GHz"

With current forms of RDRAM, we use a 400MHz external memory clock (created by the DRCGs.) The DDR technology makes this an 'effective' 800MHz. With Yellowstone on a 400MHz external memory clock, the memory operates at an 'effective' 3200MHz. With Yellowstone on a 600MHz external memory clock, the memory operates at an 'effective' 4800MHz. I fail to see any 2.4GHz bus outside of the memory modules themselves, for which they already have working samples. Are you pulling figures from nowhere? Just because I missed one of your errors does not mean I am going to miss them all.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Ncogneto

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I fail to see any 2.4GHz bus outside of the memory modules themselves, for which they already have working samples.
To properly use all 76.8GB/s of memory bandwidth would require a 64-bit FSB with an effective rate of 9.6GHz. The Pentium 4 has a 64-bit FSB that currently operates at 400MHz. If instead of a multiplier, a divider was implemented, we could set the CPU's divider to 3 and have it running at 3.2GHz on a 9.6GHz FSB.
To refresh your memory you were actually trying to implement a 9.6 ghz fsb.

Video editing?? Ha, I don't even own a camera!
 
G

Guest

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Hey I'll do it for 75K/year. Haha, but seriously, it probably depends on where you are, but around here a good engineer can be had for under 100K/year. Depending on your situation, you also probably need to rig him up with some software and test equipment, but once you buy that you will always have it. You just get a specialist to do one little tiny corner of the layout and use your old guys to do what they've been doing the whole time on the rest of the design. That's probably worst case. I can't see a memory subsystem design taking more than a couple months at most, so you could probably subcontract someone.

A big salary for sure, but I'm guessing it's small potatoes compared to the profits a popular M/B could potentially draw. Imagine being able to claim your motherboard has 10-20 times the memory performance of your competitors boards. All the server houses would deffinitely want it, especially if you made sure it did SMP correctly. I would be drooling over something like that, I'm sure others wold notice it too.
 

Raystonn

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First off, that was only a suggestion on how it might be incorporated into a Pentium 4 platform. It is much more likely that such memory bandwidth would be incorporated into a processor with a much larger frontside bus.

Second, Intel would have no problem running a frontside-bus at 9.6GHz. We already have working research samples that do this.

Third, I still do not see from where this 2.4GHz bus figure comes, especially in relation to the given alternative of 133MHz. The Pentium 4 has a 400MHz frontside-bus, not 133MHz, so he was not referring to a frontside-bus speed. Where did he get this number?

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Ncogneto

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The Pentium 4 has a 400MHz frontside-bus, not 133MHz, so he was not referring to a frontside-bus speed. Where did he get this number?
Actually the p4 has a quad pumped 100 mhz fsb ( not a 256 bit fsb either)giving it an effective fsb of 400 mhz . Please be aware that this is done internally ( inside the processor ).

We are talking about the dynamics that would need to be incorporated into the motherboard design to support these ghz buss'es.


Video editing?? Ha, I don't even own a camera!
 

Ncogneto

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Yup, sure, but as they say seeing is believing....and is this research sample with a p4? don'tr tell me let me guess another NDA?

Video editing?? Ha, I don't even own a camera!
 

Ncogneto

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Err, no, you misunderstood. What I meant was how much would this motherboard capable of supporting these ghz busses cost, not how much the engineer that designed it would make.

Video editing?? Ha, I don't even own a camera!
 

Raystonn

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The external clock on the motherboard is 100MHz. Hence the rate of clock impulses on the bus is 100MHz. The frontside-bus of the processor uses a form of QDR to achieve an effective 400MHz. That is, 64-bits of data is transmitted 400-million times per second. The rate of data transfer on the FSB is 400MHz. We use the rate of data transfer to label it and hence call it a 400MHz System Bus.

The same principle is used to identify PC2100 SDRAM as 266MHz and PC800 RDRAM as 800MHz. It is the rate of data transfer. The actual clocks are only present to facility the transfer of data. The rate of data transfer is the important measurement.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Raystonn

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"What I meant was how much would this motherboard capable of supporting these ghz busses cost, not how much the engineer that designed it would make."

I never said it would be cheap. The best (material) things in life tend to be expensive.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Ncogneto

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The external clock on the motherboard is 100MHz.
correct!

The frontside-bus of the processor uses a form of QDR to achieve an effective 400MHz.
again correct but please be aware that this is done withing the processor.

The rate of data transfer on the FSB is 400MHz
not exactly, the rate of data transfer between the processor and the MCH is 400 mhz.

Video editing?? Ha, I don't even own a camera!
 

Ncogneto

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well you said the technology would be available to the pc industry. PC stands for personal computer, typically this would mean a home computer. How many people would be able to afford this extradoniarily expensive PC and would it be worth the effort of designing it considering it would be out of almost everyones price range?

Video editing?? Ha, I don't even own a camera!
 

Raystonn

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"not exactly, the rate of data transfer between the processor and the MCH is 400 mhz."

The path between the processor and the MCH <b>is</b> the frontside-bus, also known as the System Bus on the Pentium 4. Thus the rate of data transfer on the FSB is 400MHz.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Ncogneto

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Sorry I did not explain myself suffiently. No, the effective FSB is 400 mhz...but it is still 100 mhz!!!!!!!!! PERIOD!!!!!!! Data is exchanged on both the leading and falling edges of both sides of the wave, thus 4x per 100 mhz wave. This, anyway you stack it is still a 100 mhz wave!

Video editing?? Ha, I don't even own a camera!
 

Raystonn

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"How many people would be able to afford this extradoniarily expensive PC and would it be worth the effort of designing it considering it would be out of almost everyones price range?"

Neither you nor I know how much this will cost. It might be cheap. It might be expensive. But the price does not dictate whether or not the technology is available to CPU manufacturers. It only dictates whether or not they decide to use it.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Raystonn

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"No, the effective FSB is 400 mhz...but it is still 100 mhz!!!!!!!!! PERIOD!!!!!!! Data is exchanged on both the leading and falling edges of both sides of the wave, thus 4x per 100 mhz wave. This, anyway you stack it is still a 100 mhz wave!"

I am not measuring the 'wave' here. As I said, I am measuring the data transfer rate. Data is transfered at a rate of 400MHz. This means the full width of the bus (64-bits) is transferred 400 million times per second. Performance is measured by the data transfer rate, not the rate of a clock. In the future we may not even have clocks.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

Ncogneto

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In the future we may not even have clocks.
entirely differnt discussion lets not even open up that can of worms.

I am not measuring the 'wave' here. As I said, I am measuring the data transfer rate. Data is transfered at a rate of 400MHz. This means the full width of the bus (64-bits) is transferred 400 million times per second. Performance is measured by the data transfer rate, not the rate of a clock.
I have no problem with that. However when we need to boost that carrier wave from a 100 mhz quad pumped wave ( effectie 400 mhz ) to a 2.4 ghz quad or octel pumped wave we open up pandora's box of PCB nightmares. This has been my point from the start.


Video editing?? Ha, I don't even own a camera!
 

Raystonn

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Agreed here actually. For the 64-bit Pentium 4 FSB you would need a 2.4GHz external clock to produce the 9.6GHz data transfer rate. (Perhaps this is where he got the 2.4GHz figure? Who knows.) However, this kind of bandwidth would be best suited to an FSB of 128-bits or 256-bits. A 256-bit quad-pumped FSB would require an external clock of only 600MHz and would achieve a data transfer rate of 256-bits at 2.4GHz. This would provide 76.8GB/s of bandwidth to the processor. This is feasible.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =
 
G

Guest

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The cost of the boards is the same. The R/D is the only thing that costs more here.

The PCB's cost exactly the same as a regular PCB to manufacture because they are regular PCB's. The manufacturing process is identical. The only physical differences necessary would be the actual high speed signal traces, they would have funny shapes. The manufacturing plant only sees a photo file they could care less what it looks like, or what it's for. The people doing the manufacturing certainly wouldn't know the difference, but might notice that these boards have odd looking traces. Unfortunately for them they don't charge any more for funny looking traces.

This is the beauty of the engineering formulas for microstrip (for example). The material properties are accounted for by the formulas. All that is left for the board designer is apply the formulas to his application. All the necessary trace dimensions etc. fall out of the formulas.
 

Ncogneto

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However, this kind of bandwidth woudl be best suited to an FSB of 128-bits or 256-bits. A 256-bit quad-pumped FSB would require an external clock of only 600MHz and would achieve a data transfer rate of 256-bits at 2.4GHz.
Ok now I am lost in your terminology, but I think I understand what you are getting at. The p4 and the athlon have a 64 bit memory bus ( single channel). The alpha has a dual channel ( 128 bit ) memory bus. What you are suggesting is a quad channel memory bus. Possible yes, but not by 2004, unless Intel has something up its sleave.

Video editing?? Ha, I don't even own a camera!
 

Ncogneto

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You got other issues to contend with as well not only the motherobard traces. You have to have a MCH capable of operating at 9.6 ghz ( by 2004 mind you) then you have to worry about interference as well. Not may users will appreciate the blue screen of death everytime there cordless phone rings.

Video editing?? Ha, I don't even own a camera!
 
G

Guest

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"we open up pandora's box of PCB nightmares"

not quite a Pandoras box. free, dammit, it's free. except for the engineering.