Archived from groups: comp.sys.ibm.pc.hardware.chips (
More info?)
On Wed, 02 Feb 2005 08:36:21 -0500, Yousuf Khan <bbbl67@ezrs.com> wrote:
>da_test wrote:
>> Secondly, as I mentioned in another post in this thread,
>> in my bios SPD seems related to interleave only,
>> unless I'm misunderstanding something - but I don't
>> think I am. I checked the chipset values using wpcredit.
>> Dave
>
>Why do you think that's the case? The SPD has nothing to do with
>interleave. The interleave is a factor that the system itself sets
>through the BIOS & chipset, but it runs the RAM at whatever settings you
>specified whether it's interleaved or not. Interleaving is outside the
>control of each individual DIMM, it works at the memory bank level.
Not sure what you're saying there but interleaving, as it applies to modern
DIMMs, works at the memory chip level - all SDRAM chips >16Mb used in PCs
have 4 banks right on the chip; the 16Mb chips had 2 banks. Years ago,
Dave T told me that there was a plan to go to 8 banks with 256Mb[IIRC]
chips but I guess it fell victim to backwards compatibility with chipsets,
chipset cost... or maybe even inertia.
The DDR SPD doc I have, from IBM, is old and maybe out of date but it seems
to show that there are fields in SPD for both "physical banks" on the
module, for which the term rank is preferred now, and the SDRAM device
banks. In fact the device banks field caters for going to 255 banks;
oddly, the "rank" fields cater for having different sizes of memory on each
side of a module and even different sized and width chips.
When you set the "interleave" in BIOS Setup it's the control on device
banks which you are setting: 0/off, 2 or 4. Off just runs the chips with
auto-precharge. The different chipsets have different ways of handling
this device interleave of banks: on their better chipsets, Intel has
generally allowed all 4 banks on every rank to be kept open simultaneously
and favored an idle timer for precharge; VIA has generally allowed only 2
ranks to have open banks simultaneously and precharged when an address went
to a 3rd rank. In the absence of docs, I've no idea how nVidia handles
things nor AMD.s 64s but I haven't tried to ferret that out.
BTW, I believe that device banks is/was one of Rambus' infringement claims
against SDRAM - their DRDRAM devices had 32 banks of which 16 could be open
simultaneously - the sense amps were shared between adjacent banks. They
also proposed changing to a different scheme for their later DRDRAM, with 4
"independent" banks, just like SDRAM, but I beleive it was abandoned due to
lack of interest by chipset mfrs, notably Intel.
--
Rgds, George Macdonald
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