Abit a17 no post

[sylvan]

replaced a power supply (new) and now the m/b won't power up. led on m/b goes to C0 or CF. checked voltage and they are fine. doesn't even seem like it is doing the post I know I probably sound like a moron, but just give me a place to start troubleshooting.

thx
paul

 

[shortstuff_mt]

What does your motherboard owners manual say about the C0 and CF error codes? Did you remember to plug in both the main 24-pin motherboard power connector as well as the 4/8-pin CPU power connector when you replaced the PSU?

This checklist was created to troubleshoot problems like yours. You should go through every step in the checklist.

http://www.tomshardware.com/forum/261145-31-read-posting-boot-problems

 

[sylvan]

What does your motherboard owners manual say about the C0 and CF error codes? Did you remember to plug in both the main 24-pin motherboard power connector as well as the 4/8-pin CPU power connector when you replaced the PSU?

This checklist was created to troubleshoot problems like yours. You should go through every step in the checklist.

http://www.tomshardware.com/forum/261145-31-read-posting-boot-problems

thx, unfortunately i don't have the manual. abit search doesn't even show the a17 as a valid mother board, which doesn't make sense. i hooked up the new p/s the same way (wrote it down), including the 4 pin connector.

if i can find the manual online that would be great

 

[sylvan]

great checklist guys! found the manual in the abit archives

the codes I see during power on are 83 and then goes to C0. seems to be a problem with the bios,
but I tried resetting cmos using jumper and remove battery methods with no change. any ideas?

83 save all data in stack back to CMOS

CF, C0, C1 in POST code definition table are all grouped together in 1 box like this:

CF test CMOS r/w functionality
early chipset initialization:
C0 -disable shadow ram
-disable L2 cache (socket 7 and below
-program basic chipset registers
detect memory
C1 -auto-detection of dram size,type, and ecc
-auto-detection of L2 cache (socket 7 and below)