HyperTransport (HT) is just a type of interconnect AMD uses in their CPUs to provide wider (
not faster) bus between CPU, RAM, and other system components. HT3 is just the third iteration of such protocol. To learn more, you can go to HyperTransport Consortium's website.
http://www.hypertransport.org/tech/tech_htthree.cfm?m=3
Basically, HT3 enabled Phenom have much more bandwidth than the previous generation of Athlon X2s, going from 22.4Gb/s to 41.6Gb/s. So far, HT3 is only implemented on Phenom, but not Barcelona.
I'm not exactly sure why would AMD implement HT3 on Phenom, but not on Barcelona. Desktop applications rarely consume much bandwidth compare to server applications. This is also the reason why Intel can utilize age-old interconnect technology like FSB, but still manage to outperform AMD on all front.
HT3 especially has a lot of benefits in multi-socket servers (2~4 or more CPU). Due to the nature of the system architecture, multi-socket servers usually suffer from NUMA effect (none-uniform memory architecture). This means since memory banks are shared among CPUs, if CPU0 have to access the memory bank for CPU1, system will suffer great latency just from going to CPU1, retrieve the data, and send it over to CPU0's memory bank. As a result, the benefit of having a wider bus means more data can be transferred during a clock cycle, thus reducing the total amount of time during the transfer.
This is all I know in regards to HT3. If you want to know more, you can look for MU_Engineer. He's an expert in this area
.