News Adata Teases First SMI-Powered PCIe 5.0 SSD, New CXL DDR5 Card

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Dec 24, 2005
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You are really talking about an item that the controller wont even go into production for over a year, and thats if there is no delays? So its summer 2024, AT BEST.
 
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mikewinddale

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but they [CXL memory] are reserved for custom orders for large hyperscalers and the like, so you won't see them at retail.

I hope that someone makes them retail. I needed 512 GB of RAM for a research project, but most of the time, I only need about 64 GB. So I had to build a ThreadRipper Pro system with some hella expensive RDIMMs, even though most of the time, a Ryzen would suffice for me.

It would be nice to be able to build a consumer-grade Ryzen system with a more pedestrian amount of RAM (say, 128 GB), and then install 512 GB of slower CXL for the rare time that more RAM is needed. I assume that the PCIe 5.0 x4 CXL will be cheaper per GB than straight DDR5 DIMMs.

AMD says it is bringing CXL to consumer CPUs, so I would love to be able to pair a Ryzen with ECC DIMMs and CXL memory. https://www.tomshardware.com/news/amd-working-to-bring-cxl-technology-to-consumer-cpus
 
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bit_user

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You are really talking about an item that the controller wont even go into production for over a year, and thats if there is no delays? So its summer 2024, AT BEST.
I find it rather perplexing they've announced and are showing a prototype of a product that won't be available for over a year. It makes me wonder if someone made a mistake on the year, and it's just getting copied/pasted everywhere.
 

InvalidError

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I assume that the PCIe 5.0 x4 CXL will be cheaper per GB than straight DDR5 DIMMs.
The CXL memory itself will likely be more expensive due to the need for a special PCIe-DDR5 bridge chip. You would save on the total platform cost from not needing to go server/TR4Pro to get the extra memory assuming consumer platforms can talk CXL.

As for going consumer, I have been hypothesizing for a few years that once Intel and AMD start putting 8+GB of on-package memory of some sort (ex.: HBM stacks with the 'base die' functionality embedded in the active interposer or the HBM dies stacked directly on IOD/CCD/GCD/etc. dies to reduce costs and latency), DDR5/6 may get dropped in favor of extra PCIe/CXL lanes for CXL memory or other uses.
 
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Who cares? This is adata we’re talking about. And I will never buy one no matter what they say or do because they’re hot garbage and they always will be.
 

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