News AMD 16-core Zen 5c die shots show long, narrow CCX, all 16 cores sharing a single L3 cache

[Admin]

Die shots of AMD's new Zen 5c die have been exposed, revealing a drastically different design compared to Zen 4c, featuring a single-CCX design with a highly elongated shape.

AMD 16-core Zen 5c die shots show long, narrow CCX, all 16 cores sharing a single L3 cache : Read more

 

[Elusive Ruse]

I would definitely consider upgrading next generation if that’s the case.

 

[drajitsh]

I thought zen "c" cores had reduced cache and execution resources.
Can someone clarify the exact differences between zen 5 and zen 5c cores @tomshardware

 

[drajitsh]

I thought zen "c" cores had reduced cache and execution resources.
Can someone clarify the exact differences between zen 5 and zen 5c cores @tomshardware

I thought zen 5c cores had only a 1 MB/core L3 cache

 

[Gillerer]

"C" stands for cloud-optimized; improved efficiency for die area and power, as well as increased core counts.

Cache takes up lots of space, so "C" CCDs have less of it per core.

While the architecture is exactly the same as regular Zen 5, the cores are build denser, so can't clock as high. But lower clocks mean better efficiency. (They're also guaranteed to run at that set speed 24/7, so cloud providers can be secure in selling that performance level to their customers.)

Having more cores, but at reduced performance per core may also alleviate any bottlenecks from the Infinity Fabric link to the CCD, and 12-channel DDR5. You probably couldn't realize much improvement from having 16 Zen 5 (non-C) cores on a CCD, since they'd end up being bandwidth starved.

The C-core CCDs end up being smaller enough that you can cram 1.33 to 1.5 times as many C cores per socket. Then a cloud provider gets cost savings from being able to serve more customers per rack; each running a virtual server utilizing just 1 or a few cores.

 

[AI Jedi]

I don't see how calling the C cores the equivalent of Intel's E-cores's is applicable. Also note that the E-Cores in Intel's new Arrow Lake CPU's and Lunar Lake mobile CPU's are much better than those in Intel's 13th and 14th Gen chips.

https://chipsandcheese.com/p/skymont-intels-e-cores-reach-for-the-sky

Lion Cove: Intel’s P-Core Roars

Intel’s mobile CPUs have undergone massive changes over the past couple generations as Intel defends its laptop market against AMD, Qualcomm, and to a lesser extent Apple.

chipsandcheese.com

Zen5c cores have much better floating point performance then the new e-cores

 

[Rob1C]

They'll need to make the processor skinnier, as there's barely enough room for 24 DIMMs in a dual socket 19" rack; unless they plan on returning to 23".

 

[usertests]

I would definitely consider upgrading next generation if that’s the case.

'C' chiplets have been used only in Epyc so far. We now know that Zen 6 will use 12-core chiplets for up to 24 (main) cores.

I thought zen 5c cores had only a 1 MB/core L3 cache

While the 8 Zen 5c cores in Strix Point only had 8 MiB, there is no rule saying that they can't use more cache.

'C' cores are smaller than regular cores even if you take L3 cache out of the equation. They use different cell libraries and other tricks to shrink the core.

The Zen 4c chiplet also has 16 cores and 32 MiB of L3 cache, same as this chiplet. The difference was that it was divided into two core complexes with 8 cores and 16 MiB each. Though that is still 2 MiB/core.

 

[reflex25]

The cache needs to be shared to ensure coherence.