The Inq has some interesting info on AMD's upcoming quad core cpus:
http://www.theinquirer.net/?article=31649
That's because the Athlon's are not bandwidth-starved like intel's offerings.
http://www.theinquirer.net/?article=31649
The chat quickly turned to one of those never ending complaints about vendors' CPU design approaches. So, while Intel's Core 2 Duo and upcoming Core 2 Quad (Kentsfield, Clovertown, Tigerton) are at least generous with their cache sizes, to augment somewhat for the FSB headache, it seems that AMD doesn't seem to be a cache spendthrift in their future designs - more like a THRIFT only.
That's because the Athlon's are not bandwidth-starved like intel's offerings.
I do hope this is the K8L they're talking about. And about the cache concern pointed by the author, I do think AMD is really confident about their processors not needing huge amounts of it. I do believe they have redesign the cache hierarchy since a great processor design doesn't needs enormus amounts of cache (can't say the same for intel) :roll:Look at the first example, the "Deerhound" quad-core CPU based on the K8L core tune-up, which AMD is supposed to ship in volumes during the 3rd quarter of 2007. This Opteron-class server CPU has only 2MB of shared L3 cache according to my deep throat - less than the L2 cache on the current Woodcrest! if each core has its own 1MB L2, and there are four of them, what extra use is such a small common L3 for? Well, two answers - one is to remove the inter-core and cache coherency traffic from the crossbar and keep it within that L3 cache. And the other? Well, AMD might again rely on "exclusive" cache policy, not copying the data from L2 into L3 in this case, but keeping additional code and data there.
This guy still compares AMD's approach to that of intel's.Further in mid-2008, using the same 65 nm process, AMD refreshes its line with new quad-core parts: "Cerberus" high-end Opteron MP, and "Wolfhound" Opteron DP. While Cerberus enjoys a larger (but still somehow weak) 6 MB L3 cache together with fast 2.4 GHz HyperTransport 3 (19.2 GB/s bandwidth per link, to match the built-in DDR3 memory controller speed), its DP cousin still sticks with paltry 2 MB L3 - and, hey, that is mid 2008 period!
Yeah, sure. Toy benchmarks like superpi.I really hope AMD rethinks this approach - while, yes, they do have the HyperTransport advantage (but, keep in mind, they don't OWN the whole standard), Intel's approach with Kentsfield / Clovertown / Tigerton in 6+ months gives them the dual 4 MB on die L2 caches, and memory disambiguation, somewhat absorbing the penalty of slow shared FSB. This might allow Intel to win on some benchmarks even with this early quad-core bolt-on job. Not to mention the 2008 "Bloomfield" native quad-core part with Nehalem (Core 3?) cores inside... µ