News AMD 3D V-Cache Tests Reveal Minimum Latency Increase

[Admin]

Chips and Cheese tests the latency on AMD's EPYC 7V73X (Milan-X) with 3D V-Cache.

AMD 3D V-Cache Tests Reveal Minimum Latency Increase : Read more

 

[JayNor]

Intel has 408MB L2 SRAM on Ponte Vecchio.

 

[wifiburger]

being a limited product and only one SKU I'm not really impressed,

but... there's some recent news/post that 13th Gen Intel will come with 68mb cache

 

[Alvar "Miles" Udell]

The question is how much this increases the costs. Epyc and Threadripper it's basically irrelevant. Ryzen wise, if the average benefit is 5% and there are more than a few negative cases, and that benefit is only seen at 1920x1080, that's going to make pricing tricky.

 

[samopa]

How about heat dissipation ?
I know that stacking chip over another has been done in some times, but now we're talking about stacking memory chip (relatively cool) on top of processing/computing chip (relatively hot). How the heat from the computing chip can dispersed without affecting the memory chip on top of it ?

 

[TechLurker]

Considering that they did test a 5900X3D, having both a 5900X3D and a 5950X3D SKU makes sense; helping to end AM4 on a high note while still competing well with Intel's own transitory offerings. But the 5800X3D makes more sense in the near-term simply because that one uses only one CCX die vs the two that the 5900X/5950X would use, and the binning doesn't have to be as "perfect" as the bins for the higher models. Thus, having the 5800X3D released ahead helps make use of early and less-efficient 3DV-enhanced CCXs while building enough stock of "flawless" bins for eventual 5900X3D and 5950X3D models.