IIRC Bergamo, Zen4c in server CPUs, each core is supposed to have performance around Zen 3. Gracemont has performance of about Skylake. Zen 2's IPC was 7-10% higher than Skylake and Zen 3 is another 15% over Zen 2. Based on that we could expect Zen4c's IPC to easily be 25-30% higher than Gracemont. I assume that Zen4c would be easier to clock higher as well. This could be an interesting setup as you still would have full fat cores just lower performing. It would be more like the newer Arm big.little with 4 high performance cores but 2 are clocked higher than another 2.
More than that possibly. Zen 3 IPC might be understating it. If the L3 cache is very heavily used as in HPC or gaming or similar yeah it is Zen 3 IPC but there are many everyday situations where more cache does not improve
It seems like you mean "homogeneous", not "heterogeneous".
Refer to ARM, heterogeneous means two different architectures but share the ISA, on a technical level Zen 4c is "different" but is more optimized for lower clocks
That was meant as a hyperbole, sadly there isn't a good way to express that in text.
I wouldn't say that gives us the base frequency and TDP but not the max power TDP. We both know Intel would likely try and have it boost as far as possible and throw power draw out the window, see Intel using the 5000W chiller demo system, and the actual boost TDP will be 500ishW.
I'm not following what you are getting at here as my original comment was dealing with power. Core does a good job of scaling performance with additional power draw where as Zen4 levels off VERY quickly at 105W. That said the Core CPU needs 2x the TDP for the same performance. Which goes hand in hand with my statement that Core isn't efficient.
Golden cove is a big fat core for HPC and doesn't scale down at low power, Zen 4 is not a big fat core but somehow manages to hang in there with Golden cove
I assume base frequency is given for AVX512 situations given how much AVX512 lights up big parts of the core and draws a lot of power, in server situations TDP is heavily limited
There is nothing to optimize,
some workloads can use "infinite" cores so they would be scheduled on all available cores and some workloads can only use a very limited amount of cores so they would be scheduled on the big cores, there is nothing more they can do.
Any attempt to make workloads that use fewer cores use more cores is already being done anyway.
Both of these options are pretty bad for AMD because it will increase their cost by a lot and decrease the money they would get from each CPU and they are tied to TSMC so it's not like they can just easily produce a larger amount of CPUs to compensate for the lower per unit cost.
Actually heavy customization by Intel is also going to be bad for their IDF model. Intel is currently still having troubles because they used to depend on the fab to fix their issues rather than verifying that it works (IDF model means the design team is unable to do it anymore at least on the same scale)
That said, 4x Zen 4c cores will deliver near zen 4 IPC unless its VERY cache dependent (meaning it goes into L3) and its more power optimized (the aim for them was to go into bergamo which was designed to not go high on clocks, unlike Zen 4 whos aim is HPC) while being almost half the size of Zen 4 cores. the key difference is only slashing of L3 cache
While gracemont may be more area efficient (1 golden cove = 4 gracemont) , Zen 4 is actually smaller than Golden cove cores anyway and zen 4 is more power/performance efficient than either golden cove or gracemont (gracemont very much isn't, if you have to keep the cores on longer because the IPC is poor and power draw is still mid, it ends up drawing quite a lot more than expected in joules)
Not to forget that Intel bakes in L3 in the golden cove but not the gracemont means that anytime the gracemont cores are to be used, data has to exit the gracemont cores, light up the whole ring, look for data in the golden cove L3 because its not a true system level cache, uncore power draw is also significant