News AMD announces 3nm EPYC Turin launching with 192 cores and 384 threads in second half of 2024 — 5.4X faster than Intel Xeon in AI workload

[Admin]

AMD CEO Lisa Su announced at Computex 2024 that the company's next-gen EPYC Turin chips for the data center will launch in the second half of 2024.

AMD announces 3nm EPYC Turin launching with 192 cores and 384 threads in second half of 2024 — 5.4X faster than Intel Xeon in AI workload : Read more

 

[hotaru251]

AMD will never let Intel back in server performance at this rate.

amd already onto next race while intel just crosses the finish line of last one.

 

[Deleted member 2731765]

Here are some 20 Turin SKUs based on the Zen 5 & Zen 5C core architecture, branded under the EPYC 9005 family.

The 192 core flagship part is missing here though, and since there's no mention of which of these SKUs are based on the Zen 5 or Zen 5c architecture, we can make some educated guess, also based on the L3 cache.

IMO, seems unlikely that there will be Zen 5c offerings above 128 cores, so 144-core and 160-core variants should stick with the Zen 5C architecture.

EPYC Zen 5C: Up To 192 Cores.

EPYC Zen 5: Up To 128 Cores.

EDIT:

The EPYC 9005 series branding was actually confirmed in a latest submission by AMD at SATA-IO.

https://sata-io.org/product/9044

 

[bit_user]

AMD will never let Intel back in server performance at this rate.

amd already onto next race while intel just crosses the finish line of last one.

Intel will allegedly counter with 128-core Granite Rapids and answer the 192-core/384-thread Zen 5c version with 288-core/288-thread Sierra Forest:

https://www.tomshardware.com/pc-com...-breathing-128-core-granite-rapids-xeon-6-cpu
​

I'm not saying Intel will match AMD in perf/W, this generation, although it's going to be Intel 3 vs. TSMC N4 N3B (?). So, even if they don't completely catch up, they should at least have narrowed the gap quite considerably.

 

[thestryker]

This ought to be the most interesting enterprise level has been since Zen 2 based Epyc launched. Interesting to see how well AMD has optimized Zen 5 that they didn't need to jump to N3 for the standard CCDs which undoubtedly helps the financial side of things.

 

[peachpuff]

Poor intel...

 

[TechyIT223]

Rich 🤑 Intel

 

[dalek1234]

"AMD's Zen 5c architecture...density-optimized cores that are conceptually similar to Intel's e-cores"

No, they are not. Intel castrated their cores to make them smaller. AMD packed the transistors closer together and reduced cache size. From instruction stand point, Zen 5 and Zen 5c are identical, which is not the case with Intel's e-cores (Also refereed to as Garbage Cores)

 

[abufrejoval]

"AMD's Zen 5c architecture...density-optimized cores that are conceptually similar to Intel's e-cores"

No, they are not. Intel castrated their cores to make them smaller. AMD packed the transistors closer together and reduced cache size. From instruction stand point, Zen 5 and Zen 5c are identical, which is not the case with Intel's e-cores (Also refereed to as Garbage Cores)

Castration takes something away that was originally there. Not the case with e-cores, they are a distinct design for the same ISA, sometimes with a subset (still no castration).

Yes, turning off the AVX512 IP blocks on Alder Lake P-cores probably qualifies as castration.

And for the AMD compact core approach, a half sized cache might actually fit your use of "castration" and result in significant penalties for cache sensitve workloads. That's why hyperscalers will carefully test and tune.

But the genius is that a lot of the silicon surface area which has to be left dark for cooling on top-clock desgns, can instead be filled with logic on a design with lower max-clocks, resulting in less area waste.

Or well, it would be genius, if it wasn't quite simply what Ampere and similar hyperscaler specific designs had already been doing first.

If now they could only make chips switch between those two personalities on the fly!

And I guess dynamically disabling/not using hyperhreading to gain some clocks would get you half way there?

 

[bit_user]

"AMD's Zen 5c architecture...density-optimized cores that are conceptually similar to Intel's e-cores"

No, they are not.

FWIW, I'd characterize it as a different solution to the same problem of trying to increase compute density and efficiency.

Intel castrated their cores to make them smaller.

If we're nit-picking, I wouldn't even say that. What they did was to use a fundamentally different core design, from a completely different lineage.

https://en.wikipedia.org/wiki/Intel_Atom
​

AMD actually had their own lineage of E-cores, but that ended with the advent of Zen.

Puma (microarchitecture) - Wikipedia

en.wikipedia.org

AMD packed the transistors closer together and reduced cache size.

At the expense of clockspeed, which explains why they weren't so densely-packed in the non-C version. That's a big reason why the C-cores are smaller - possibly even bigger than the cache reduction.

From instruction stand point, Zen 5 and Zen 5c are identical, which is not the case with Intel's e-cores (Also refereed to as Garbage Cores)

They're not garbage. They offer good compute density, which is what they were designed to do. You might disagree with how they were used in a particular product line, but that doesn't make them outright garbage.

 

[frogr]

Intel will allegedly counter with 128-core Granite Rapids and answer the 192-core/384-thread Zen 5c version with 288-core/288-thread Sierra Forest:

​

https://www.tomshardware.com/pc-com...-breathing-128-core-granite-rapids-xeon-6-cpu​

​

I'm not saying Intel will match AMD in perf/W, this generation, although it's going to be Intel 3 vs. TSMC N4. So, even if they don't completely catch up, they should at least have narrowed the gap quite considerably.

Actually it is granite rapids on intel 3 with E cores vs AMD on TMSC 3nm with 5c cores

 

[bit_user]

Actually it is granite rapids on intel 3 with E cores vs AMD on TMSC 3nm with 5c cores

Yes, but which 3nm node? Seems like N3B, from what I can tell.

 

[Jimbojan]

I am sorry, Intel will be more power efficient than AMD's (4nm TSMC) if Intel is using its 3nm fab. If Intel is doing 128 core at 3nm now, it will use 18A in 2H24, AMD will be at least 6 months behind Intel. When Intel was doing 7nm, AMD was using 5nm TSMC, the server chips were about even in power efficiency, that is Intel is always doing better to manage its chip power than AMD's. Now that AMD is falling behind in nm fab due to TSMC, AMD will never able to compete in power efficiency, as Intel leaps ahead. Unless Intel falters again, it is not likely in the current environment.

 

[helper800]

I am sorry, Intel will be more power efficient than AMD's (4nm TSMC) if Intel is using its 3nm fab. If Intel is doing 128 core at 3nm now, it will use 18A in 2H24, AMD will be at least 6 months behind Intel. When Intel was doing 7nm, AMD was using 5nm TSMC, the server chips were about even in power efficiency, that is Intel is always doing better to manage its chip power than AMD's. Now that AMD is falling behind in nm fab due to TSMC, AMD will never able to compete in power efficiency, as Intel leaps ahead. Unless Intel falters again, it is not likely in the current environment.

As stated above AMD will be on one of TSMC's 3nm nodes. When you were talking about intel 7nm and AMD 5nm, could you qualify your statement about the two companies products being at the same power efficiency? To my knowledge, AMD was moderately more performance per watt. To say that AMD is losing in the server sector at this point sounds fishy to me, but hey, I know little of the server sector.

 

[bit_user]

I am sorry, Intel will be more power efficient than AMD's (4nm TSMC) if Intel is using its 3nm fab.

Power efficiency is about a lot more than just the fab node. With that said, you also got the fab node wrong for the Zen 5C chiplets (as helper800 pointed out).

If Intel is doing 128 core at 3nm now, it will use 18A in 2H24,

No such server CPU is planned in that timeframe. As far as I know, Panther Lake would be the first thing that could use it, and that's not planned to launch until 2025.

When Intel was doing 7nm, AMD was using 5nm TSMC, the server chips were about even in power efficiency,

Not even remotely true. Countless EPYC vs. Xeon benchmarks have shown Zen 4-era AMD CPUs utterly crushing Sapphire Rapids and even Emerald Rapids Xeons! The only answers Intel has mustered involve some narrow benchmarks that highlight AMX or their other accelerators, but those don't represent typical server workloads.

AMD will never able to compete in power efficiency, as Intel leaps ahead.

You seem to pop up to plug Intel products, every now and then. I don't know what your stake in the matter is, but I have yet to see an unbiased take from you.

 

[thestryker]

No such server CPU is planned in that timeframe. As far as I know, Panther Lake would be the first thing that could use it, and that's not planned to launch until 2025.

May have meant 2025 which would be mostly believable for CWF.

 

[DaveLTX]

Did nobody catch that the writing has the chiplet count reversed?
Turin Dense has 12 ccds
Turin has 16 ccds

 

[bit_user]

Did nobody catch that the writing has the chiplet count reversed?
Turin Dense has 12 ccds
Turin has 16 ccds

I guess I assumed it must be something like that, given that regular Zen 5 chiplets still have 8 cores per die and they need to hit a max of 128 cores. Packing 16 C-cores per chiplet is what they did in Bergamo, so I figured they'd probably still do that in Turin (dense).

 

[thestryker]

Did nobody catch that the writing has the chiplet count reversed?
Turin Dense has 12 ccds
Turin has 16 ccds

Good catch I certainly didn't notice it despite knowing that Zen 5c was 12 CCDs.

There is apparently also a 16 core Zen 5 CCD I wish I could remember which coverage I saw talking about it. I think it was something with George from Chips and Cheese, but I can't recall if it was their content. I'm curious what implementation would get those perhaps it'd be next gen Instinct.

 

[DaveLTX]

I guess I assumed it must be something like that, given that regular Zen 5 chiplets still have 8 cores per die and they need to hit a max of 128 cores. Packing 16 C-cores per chiplet is what they did in Bergamo, so I figured they'd probably still do that in Turin (dense).

They're not changing the configuration yet and it'd only make sense that they stick to that and use the same ccds as client parts
Unless for some reason a 10.67 core Z5 ccd exists
Or a 12 core Z5C when it's already pictured with 12 Z5c CCDs...
I've noticed massive errors on tomshw for a while now and they're not getting edited