News AMD Announces Threadripper HEDT and Pro 9000-Series CPUs: 96 cores and 192 threads for Desktops and Workstations

[Admin]

AMD announced its new Zen 5-powered 'Shamida Peak' Ryzen Threadripper Pro 9000 WX-series and non-Pro processors here at Computex 2025 in Taipei, Taiwan, touting up to 96 cores and 192 threads in the flagship 9995WX.

AMD Announces Threadripper HEDT and Pro 9000-Series CPUs: 96 cores and 192 threads for Desktops and Workstations : Read more

 

[Sluggotg]

Looks like a great lineup. Can't wait to see the reviews!

 

[thestryker]

It'll be really interesting to see what sort of performance Zen 5 brings to Threadripper. If it's like desktop there should be better clock scaling which should directly turn into performance.

Still tired of them calling these HEDT though as they're all just workstation processors. HEDT is dead and buried as it has been for around 5 years.

The cheapest CPU is more than double the most expensive desktop, cheapest motherboard is four times the cost of one which will run said desktop CPU and minimum price of entry for DRAM is more than double that of equivalent desktop capacity (ECC prices are close to the same, but there aren't any high performance ECC UDIMMs).

 

[Tech0000]

wow! This is great news!

Last time Intel and AMD had true X level HEDT (priced for prosumers - not the insanely expensive Xeon WS and PRO class) was in 2019 when intel launched the Core i9 109x0XE series (e.g. 10980XE) on x299 chipset competing with AMD's X corresponding HEDT: Threadripper 3970X, 3960X, 3950X.

Maybe finally we will again get a true HEDT competition between intel's X version of Xeon against AMD's 9000 series Threadripper HEDT version with similar pricing (adjusted for inflation).

Let's hope! This could be very interesting with a true successor belonging to the X platform lineage. My first X was a X58 Motherboard with a core i9 980X. X58 could also accept Xeon (pin compatible) which one could find cheap on ebay once companies upgraded and offloaded these - golden!

I suspect there are a lot of people with old x299 and similar HEDT AMD platforms out there waiting for this...

Intel now needs to answer...

 

[Elusive Ruse]

Look at the size of that thang!

 

[passivecool]

Yet another 20% generational performance increase from AMD. Boring.

 

[cracklingice]

It is really frustrating that AMD keeps trying to call Threadripper HEDT while only having the high end 24 and 32 core HEDT parts and 64 pure workstation part in the lineup. Where are the affordable 12 and 16 core parts for the enthusiasts? I was on X99 until last year because there still is not a reasonable path to upgrade from X99. If AMD had released a 16 core Zen 2 TR4 CPU - I would have bought that. If AMD had released a 16 core x3d Zen 3 CPU - I would have bought that too. And if AMD released a 16 core x3d Zen 5 CPU - I'd probably be buying that one too. Instead AMD seems to think I am a shmuck that will pay HEDT pricing for HEDT core count on the consumer socket. It's not going to happen. I want the cores but I want the I/O more.
Please AMD. Please. Bring back HEDT. I've said it before and I'll say it again. Make the next IOD in a similar way that Apple makes their M silicon. Have two dual channel 24 PCIE lane + chipset link IODs that have a high bandwidth severable connection so that you can have a proper HEDT IOD (albeit with NUMA downsides) that you can also cut in half to make consumer socket chips and make sure to have overlap with the 2 CCD SKUs. HEDT needs to actually be accessible to enthusiasts or it is not HEDT and at $2200 for just the motherboard and entry level processor - it certainly is not that.
I would also settle for finding a way to make TRX50 more reasonably priced and offering reasonably priced 12 and 16 core Threadripper non-pro chips.
I mean seriously - how did we go from people flaming intel over $1700 top of HEDT range chips while they started at $450 to calling people poor for not wanting to spend almost that former top of range price for the entry point or $2500 for the first reasonable option with full 8 core CCDs. It's bizarro world.

 

[bit_user]

Make the next IOD in a similar way that Apple makes their M silicon.

Won't happen. Apple's M-line has very poor I/O connectivity. If Apple would offer more I/O, they'd probably do the same as AMD and have a dedicated I/O chiplet. That's because I/O doesn't scale down well, so you're better off using a cheaper node for it.

For an I/O-heavy CPU, like ThreadRipper, it would be especially nonsensical to go backwards and integrate the IO in the compute dies.

$2500 for the first reasonable option with full 8 core CCDs.

Just wanted to point out that by using 6-core CCDs, the 24-core ThreadRipper has a higher cache-to-core ratio. In other words, it has the same amount of L3 as the 32-core model, but costs much less. The 7960X also has the same 4 memory channels and 48 PCIe 5.0 + 24 PCIe 4.0 lanes, all for $1.5k.

 

[cracklingice]

Still tired of them calling these HEDT though as they're all just workstation processors. HEDT is dead and buried as it has been for around 5 years.

The cheapest CPU is more than double the most expensive desktop, cheapest motherboard is four times the cost of one which will run said desktop CPU and minimum price of entry for DRAM is more than double that of equivalent desktop capacity (ECC prices are close to the same, but there aren't any high performance ECC UDIMMs).

Very strongly agree Stryker.

Last time Intel and AMD had true X level HEDT (priced for prosumers - not the insanely expensive Xeon WS and PRO class) was in 2019 when intel launched the Core i9 109x0XE series (e.g. 10980XE) on x299 chipset competing with AMD's X corresponding HEDT: Threadripper 3970X, 3960X, 3950X.

Maybe finally we will again get a true HEDT competition between intel's X version of Xeon against AMD's 9000 series Threadripper HEDT version with similar pricing (adjusted for inflation).

Let's hope! This could be very interesting with a true successor belonging to the X platform lineage. My first X was a X58 Motherboard with a core i9 980X. X58 could also accept Xeon (pin compatible) which one could find cheap on ebay once companies upgraded and offloaded these - golden!

I suspect there are a lot of people with old x299 and similar HEDT AMD platforms out there waiting for this...

Intel now needs to answer...

X299 was last HEDT from Intel and TR4 was last HEDT from AMD. AMD moved HEDT core count to consumer socket with HEDT prices and for some reason people rejoiced getting less while paying the same. Meanwhile AMD also doubled the cost HEDT used to be to make Lite Workstation. Threadripper non Pro has started at 24 cores with eye watering prices ever since Zen2 and unlike consumer socket parts does not seem to ever really get a discount.

Yet another 20% generational performance increase from AMD. Boring.

I mean, it is just moving from Zen 4 to Zen 5 after all. It's not like they were reinventing the wheel here.

 

[cracklingice]

Won't happen. Apple's M-line has very poor I/O connectivity. If Apple would offer more I/O, they'd probably do the same as AMD and have a dedicated I/O chiplet. That's because I/O doesn't scale down well, so you're better off using a cheaper node for it.

For an I/O-heavy CPU, like ThreadRipper, it would be especially nonsensical to go backwards and integrate the IO in the compute dies.


Just wanted to point out that by using 6-core CCDs, the 24-core ThreadRipper has a higher cache-to-core ratio. In other words, it has the same amount of L3 as the 32-core model, but costs much less.

You entirely misunderstood my post. I want them to fuse two IODs together to make effectively a dual socket Ryzen on a single package. By having the connection entirely in silicon it would be higher bandwidth and lower latency that way. Likely also much cheaper than trying to use another form of silicon bridge such as an interposer or embedded bridge.

Regarding your statement about the 24 core - that is true - but if you run something that would benefit from both local cache and more than 6c/12t such as a game - you run into the issue of jumping cross CCDs and the gain the latencies and cache misses associated with that. Thus why I do not want 6 core CCDs.

 

[bit_user]

You entirely misunderstood my post. I want them to fuse two IODs together to make effectively a dual socket Ryzen on a single package. By having the connection entirely in silicon it would be higher bandwidth and lower latency that way. Likely also much cheaper than trying to use another form of silicon bridge such as an interposer or embedded bridge.

I guess I'm still confused, but that's okay.

Regarding your statement about the 24 core - that is true - but if you run something that would benefit from both local cache and more than 6c/12t such as a game - you run into the issue of jumping cross CCDs and the gain the latencies and cache misses associated with that. Thus why I do not want 6 core CCDs.

So, are there games which run worse on a R9 9900X than R5 9600X? That's how you'd know whether the cross-CCD penalty is something you should worry about. I'd look for such supporting data on this, because real-world outcomes don't always match our intuition about these things.

IMO, the biggest rip-off about the 7960X is the motherboard. For the CPU, you're paying like double the price of a R9 9950X, but you get 50% more cores, double the L3 cache, double the memory bandwidth, and more than double the I/O. However, the cheapest motherboard I can find on Newegg is $900. So, that kind of stings. (Edit: there's a Gigabyte for $600, on Amazon.) And then there are the RDIMMs for it.

Anyway, it's certainly not a cheap platform to be on, but that doesn't seem way out there, to me, if you really need its capabilities.

P.S. I see some deals on refurb workstations with 7960X. That seems like the easiest way to get onto the Threadripper platform. If I really needed to, I'd probably look for such a system with a decent warranty, from a reputable seller.

 

[thestryker]

So, are there games which run worse on a R9 9900X than R5 9600X?

CP2077, Remnant II, and Spider-man Remastered (I left Starfield off because it has Zen 5 issues and I'm not sure whether or not that has been resolved), but these are definitely exceptions: https://www.techpowerup.com/review/amd-ryzen-9-9900x/18.html

Generally speaking I think most games try to stick to a single CCD so it's just 8 cores being better than 6 for things like the 9700X performing higher than the 9900X on average.

IMO, the biggest rip-off about the 7960X is the motherboard. For the CPU, you're paying like double the price of a R9 9950X, but you get 50% more cores, double the L3 cache, double the memory bandwidth, and more than double the I/O. However, the cheapest motherboard I can find on Newegg is $900. So, that kind of stings. (Edit: there's a Gigabyte for $600, on Amazon.) And then there are the RDIMMs for it.

I agree that the platform cost is bad, but so is the CPU (was going to mention the TRX50 Aero D, but you went and edited your post while I was writing 😆). AMD charged $250 retail for an extra 6 core CCD (7600X to 7900X) and the 7900X was $549 MSRP so we'd be up to $1049. I don't think the superior IO die is particularly worth $450 additional cost. I think $1199 or $1249 would have been a far more reasonable price tag for the 7960X. Even then I think an extra $150-200 is being relatively generous for the IO die, but there may also be some lower packaging yield rates.

I guess I'm still confused, but that's okay.

I can't come up with anything either.

 

[cracklingice]

I guess I'm still confused, but that's okay.


So, are there games which run worse on a R9 9900X than R5 9600X? That's how you'd know whether the cross-CCD penalty is something you should worry about. I'd look for such supporting data on this, because real-world outcomes don't always match our intuition about these things.

IMO, the biggest rip-off about the 7960X is the motherboard. For the CPU, you're paying like double the price of a R9 9950X, but you get 50% more cores, double the L3 cache, double the memory bandwidth, and more than double the I/O. However, the cheapest motherboard I can find on Newegg is $900. So, that kind of stings. And then there are the RDIMMs for it.

Anyway, it's certainly not a cheap platform to be on, but that doesn't seem way out there, to me, if you really need its capabilities.

P.S. I see some deals on refurb workstations with 7960X. That seems like the easiest way to get onto the Threadripper platform. If I really needed to, I'd probably look for such a system with a decent warranty, from a reputable seller.

I do not need to see the results to know that it is possible and is not something I want out of a CPU that is likely to be my primary machine for 4 or more years and costs more than $150. Besides, you aren't talking about a 12 core Threadripper as I have no reason to consider a CPU over 16 cores unless it was quite cheap.

The motherboards are likely in a low supply situation as they're probably preparing a new refreshed batch. There was a $600 Gigabyte board - but it only had three slots total. Two 16 lanes and one 8 iirc. Or maybe it was two gen 5 and one gen 4. It's been a while I really paid attention to the boards. I do remember that it caused Asrock to drop the price of their board by $100 and is the one I would have gone with if there was a 16 core CPU.

I would not consider a pre-built. The only prebuild I purchased was a 466mhz celeron based emachine.

 

[bit_user]

CP2077, Remnant II, and Spider-man Remastered (I left Starfield off because it has Zen 5 issues and I'm not sure whether or not that has been resolved), but these are definitely exceptions: https://www.techpowerup.com/review/amd-ryzen-9-9900x/18.html

Generally speaking I think most games try to stick to a single CCD so it's just 8 cores being better than 6 for things like the 9700X performing higher than the 9900X on average.

Thanks for the examples!

I agree that the platform cost is bad, but so is the CPU (was going to mention the TRX50 Aero D, but you went and edited your post while I was writing 😆). AMD charged $250 retail for an extra 6 core CCD (7600X to 7900X) and the 7900X was $549 MSRP so we'd be up to $1049. I don't think the superior IO die is particularly worth $450 additional cost. I think $1199 or $1249 would have been a far more reasonable price tag for the 7960X. Even then I think an extra $150-200 is being relatively generous for the IO die, but there may also be some lower packaging yield rates.

Eh, I think some price premium is to be expected, given the relatively lower volume of such a product. Could they make it cheaper? I'm sure. I just don't think it's a particularly unfair price, by my accounting.

 

[cracklingice]

I agree that the platform cost is bad, but so is the CPU (was going to mention the TRX50 Aero D, but you went and edited your post while I was writing 😆). AMD charged $250 retail for an extra 6 core CCD (7600X to 7900X) and the 7900X was $549 MSRP so we'd be up to $1049. I don't think the superior IO die is particularly worth $450 additional cost. I think $1199 or $1249 would have been a far more reasonable price tag for the 7960X. Even then I think an extra $150-200 is being relatively generous for the IO die, but there may also be some lower packaging yield rates.

I can't come up with anything either.

Honestly - I'd still be fully disinterested in a 24 core at $1200. 16 core at $900, sold.

I really don't understand why it's so hard to understand what I am say regarding the doubled up consumer IOD so I will make a pretty picture. I rotated a delided Ryzen 9 180°, erased the top half of one and slid it over to make the IOD a single piece. Imagine that the IOD is just one masked out piece of silicon and the purple line is a high bandwidth connection making it effectively a dual socket system on package. But that connection can also be cut to make two standard desktop IODs. What you end up with is the ability to make real HEDT with 12 to 32 cores, two chipsets like X670E but with their own dedicated links instead of daisy chain, 48 total PCIE lanes (though I'm sure they'd still mandate 4 for USB 4 and probably another 4 for something else like networking or heck more USB why not) and two dual channel (non registered!) memory controllers. Effectively it'd be relatively similar to the original Threadripper design but with an IOD in the middle instead of IO spread around the chiplets.

 

[cracklingice]

Thanks for the examples!


Eh, I think some price premium is to be expected, given the relatively lower volume of such a product. Could they make it cheaper? I'm sure. I just don't think it's a particularly unfair price, by my accounting.

You'd probably find it odd that I don't particularly hate the price of the 24 core. After all the $900 16 core I want to exist is the same price per core but only uses two CCDs instead of 4!
I would also point out that if they had a $750 12 core and $900 16 core Threadripper (non Pro) that the volume of sales would pick up - possibly a lot. 16 core is the top of range desktop socket, but some mad lad could build a 16 core Threadripper today for not much more than they're spending on the CPU over the cost of the entire system and have the ability to upgrade as high as 64 cores later on the used market.

 

[thestryker]

I really don't understand why it's so hard to understand what I am say regarding the doubled up consumer IOD so I will make a pretty picture. I rotated a delided Ryzen 9 180°, erased the top half of one and slid it over to make the IOD a single piece. Imagine that the silicon is just one masked out piece of silicon and the purple line is a high bandwidth connection making it effectively a dual socket system on package. But that connection can also be cut to make two standard desktop IODs. What you end up with is the ability to make real HEDT with 12 to 32 cores, two chipsets like X670E but with their own dedicated links instead of daisy chain, 48 total PCIE lanes (though I'm sure they'd still mandate 4 for USB 4 and probably another 4 for something else like networking or heck more USB why not) and two dual channel (non registered!) memory controllers. Effectively it'd be relatively similar to the original Threadripper design but with an IOD in the middle instead of IO spread around the chiplets.

Perhaps the reason it was confusing is that AMD would never do what you're suggesting. They'd just make a different IO die and call it a day as there's nothing stopping them from making one with more PCIe connectivity or wider memory bus.

I too would like to see an actual HEDT product lineup return that sits between desktop and workstation, but I just don't think we're ever going to see it again. Realistically HEDT is dead and AMD shouldn't be perpetuating the lie that Threadripper is somehow "enthusiast desktop".

 

[cracklingice]

Perhaps the reason it was confusing is that AMD would never do what you're suggesting. They'd just make a different IO die and call it a day as there's nothing stopping them from making one with more PCIe connectivity or wider memory bus.

I too would like to see an actual HEDT product lineup return that sits between desktop and workstation, but I just don't think we're ever going to see it again. Realistically HEDT is dead and AMD shouldn't be perpetuating the lie that Threadripper is somehow "enthusiast desktop".

I have no idea why you think AMD would never do that. It's minimal additional silicon for the connection and would use substantially less silicon since it appears that Threadripper non pro is using the same IOD that is used in Epyc Genoa. That chip has 12 memory channels and Threadripper only uses 4. The IOD for Threadripper also has 128 PCIE lanes while HEDT really has little use of more than 48. Oh the IOD also has CXL (though I don't think Threadripper gets access to it) and while that could be a fun toy later on when enterprises start to decommission, does that add more silicon to the IOD too?
Honestly - I see this as a win win win. No more needing to use full on Epyc server IODs and no more registered memory getting in the way of adoption as well as no reason to hesitate with 12 and 16 core options - all for a relatively small cost in design that allows for wafers with defects to be sliced into consumer IODs - or even fully working ones if you find you have simply too many HEDT IODs. Oh - and any development on consumer desktop would also carry over very simply to HEDT - unlike the server based counterpart.

 

[thestryker]

I have no idea why you think AMD would never do that. It's minimal additional silicon for the connection and would use substantially less silicon

Advanced packaging isn't free nor is it devoid of yield issues. If AMD wanted to make an in between system with less connectivity they would just design a new IO die.

Honestly - I see this as a win win win. No more needing to use full on Epyc server IODs and no more registered memory getting in the way of adoption as well as no reason to hesitate with 12 and 16 core options - all for a relatively small cost in design that allows for wafers with defects to be sliced into consumer IODs - or even fully working ones if you find you have simply too many HEDT IODs. Oh - and any development on consumer desktop would also carry over very simply to HEDT - unlike the server based counterpart.

What socket do you think these CPUs are going to use exactly? Certainly isn't going to be AM5 because there aren't enough pins and going sTR5 just means expensive motherboards.

 

[bit_user]

I really don't understand why it's so hard to understand what I am say regarding the doubled up consumer IOD so I will make a pretty picture. I rotated a delided Ryzen 9 180°, erased the top half of one and slid it over to make the IOD a single piece. Imagine that the IOD is just one masked out piece of silicon and the purple line is a high bandwidth connection making it effectively a dual socket system on package. But that connection can also be cut to make two standard desktop IODs.

How do they talk to each other? Are you reusing some of the PCIe lanes, like Zen 1 did? That would add latency, when a CCD on one IOD is talking to one on the other IOD. I think it's better to have a single, unified switch fabric. To get the full benefits of a single IO die, it needs to be non-cuttable. As soon as you dictate that it must be able to be cut, then the two halves of it need to be somewhat decoupled, and that undermines the benefits of having a single piece of silicon.

The main benefit I see for your scheme is if the market were too small for the smaller IO die, but they do have a mid-range server lineup that I think reuses the same mid-level socket and IO die (or, at least it could). I agree with @thestryker that AMD would rather just make more IO dies, if there were a benefit in doing so.

Effectively it'd be relatively similar to the original Threadripper design but with an IOD in the middle instead of IO spread around the chiplets.

I kind of liked the original EPYC/ThreadRipper's distributed I/O. I understand why the current design is better, but there was a certain elegance to that approach.

 

[bit_user]

no more registered memory getting in the way of adoption

RDIMMs enable higher capacity, via 2 DPC & quad-ranked DIMMs, as well as higher speeds. For a lot of users, the higher memory capacity is one of the selling points for ThreadRipper. Especially when you start to scale up the number of cores, you really need more memory!

Yes, there have previously been systems that supported both UDIMMs and RDIMMs, but I've never seen such a thing for DDR5. Therefore, I don't know if it's even technically feasible.

 

[cracklingice]

Advanced packaging isn't free nor is it devoid of yield issues. If AMD wanted to make an in between system with less connectivity they would just design a new IO die.

What socket do you think these CPUs are going to use exactly? Certainly isn't going to be AM5 because there aren't enough pins and going sTR5 just means expensive motherboards.

There is no advanced packaging - that's the entire point of the theoretical IOD being a single piece of silicon for HEDT but can also be cut in half to make two consumer IODs.
Regarding socket, don't know, don't particularly care. The socket on it's own cannot as expensive as people seem to think. Oh no an extra $50 or so on the motherboard cost vs how much more it would cost to design a new solution.

How do they talk to each other? Are you reusing some of the PCIe lanes, like Zen 1 did? That would add latency, when a CCD on one IOD is talking to one on the other IOD. I think it's better to have a single, unified switch fabric. To get the full benefits of a single IO die, it needs to be non-cuttable. As soon as you dictate that it must be able to be cut, then the two halves of it need to be somewhat decoupled, and that undermines the benefits of having a single piece of silicon.

The main benefit I see for your scheme is if the market were too small for the smaller IO die, but they do have a mid-range server lineup that I think reuses the same mid-level socket and IO die (or, at least it could). I agree with @thestryker that AMD would rather just make more IO dies, if there were a benefit in doing so.


I kind of liked the original EPYC/ThreadRipper's distributed I/O. I understand why the current design is better, but there was a certain elegance to that approach.

I would assume some form of UCIE but I am not an engineer tasked with designing it. The point of it being a single piece of silicon that is dual purpose is that it significantly reduces cost. There is only one design that serves both platforms. If the design cost was not a problem - they would not be using full on Epyc IODs on Threadripper non pro. There would be no advanced packaging such as embedded interconnects or interposers. I also see little problem with it being a NUMA system personally. Technically Zen and Zen+ were both NUMA. Yes, there are downsides but when it comes with the upside of being much more affordable it washes out.

RDIMMs enable higher capacity, via 2 DPC & quad-ranked DIMMs, as well as higher speeds. For a lot of users, the higher memory capacity is one of the selling points for ThreadRipper. Especially when you start to scale up the number of cores, you really need more memory!

Yes, there have previously been systems that supported both UDIMMs and RDIMMs, but I've never seen such a thing for DDR5. Therefore, I don't know if it's even technically feasible.

Threadripper Pro would still exist for those who want/need registered memory. Registered memory is great for workstations. It isn't really needed for HEDT and 32 cores (the max supported in the theoretical platform) would do every bit as well with 4 channels of UDIMMs as the 16 core does with 2.
DDR4 and likely earlier versions as well used pin compatible slots. With DDR5 UDIMM and RDIMM use different physical slots, therefore it is not possible to interchange.
I mean, yes in an ideal world the platform would magically support both like X99, the best platform ever. Mine started with 6 cores with 16GB as my desktop and is now 16 cores with 256GB as my server. I very much want that again, but AMD clearly does not want to sell 16 core Threadrippers to make my dream come true - and at the size of that IOD I understand why they would not want to cut it down that far or if they're entirely made out of partial defects then it makes even more sense as to why they don't want Threadripper to be a volume product.

 

[thestryker]

There is no advanced packaging - that's the entire point of the theoretical IOD being a single piece of silicon for HEDT but can also be cut in half to make two consumer IODs.

This wouldn't be any better because you need an interconnect that can be severed without damaging functionality. I'd imagine it would actually be a lot worse from a yield standpoint.

There's also all the wasted space for the second IGP and display output when in "HEDT" configuration (this is a problem for the dual die strategy no matter how implemented).

Regarding socket, don't know, don't particularly care. The socket on it's own cannot as expensive as people seem to think. Oh no an extra $50 or so on the motherboard cost vs how much more it would cost to design a new solution.

You should care about socket because there are only two existing options and one of them cannot be used. So you either want AMD to make an in between socket that makes sense for the usage or to use the existing sTR5. The former makes more sense from a pure manufacturing cost standpoint, but with no existing manufacturing in place is a questionable proposition given an unknown volume of sales. The latter makes a lot more sense from a manufacturing infrastructure sense, but as @bit_user pointed out earlier price of entry is $600. Even with less connectivity the chances of motherboard partners being interested in reducing costs of said platform is very low.

 

[bit_user]

There is no advanced packaging - that's the entire point of the theoretical IOD being a single piece of silicon for HEDT but can also be cut in half to make two consumer IODs.

I'm just going to suggest you show us an example, in recent history, where anyone has actually done this. If you can't find such an example where a die could literally be cut in half, how can you be sure it's even feasible or worthwhile?

Technically Zen and Zen+ were both NUMA. Yes, there are downsides but when it comes with the upside of being much more affordable it washes out.

I just want to point out that Zen/Zen+ could go directly from one CCD to another. Not CCD -> IOD -> IOD -> CCD. The penalty (and thus viability) of a NUMA implementation has a lot to do with such particulars.

started with 6 cores with 16GB as my desktop and is now 16 cores with 256GB as my server. I very much want that again, but AMD clearly does not want to sell 16 core Threadrippers to make my dream come true - and at the size of that IOD I understand why they would not want to cut it down that far

I think they just don't see a market for it. It's not as if the price would make it non-viable, or else the EPYC 9015 (list price: $527) could not exist. In fact, you could get a 16-core Zen 5 EPYC for $726 (9115) or $1214 (9135), depending on your clock speed & TDP requirements.

And with that, I'm out.

 

[cracklingice]

This wouldn't be any better because you need an interconnect that can be severed without damaging functionality. I'd imagine it would actually be a lot worse from a yield standpoint.

There's also all the wasted space for the second IGP and display output when in "HEDT" configuration (this is a problem for the dual die strategy no matter how implemented).

You should care about socket because there are only two existing options and one of them cannot be used. So you either want AMD to make an in between socket that makes sense for the usage or to use the existing sTR5. The former makes more sense from a pure manufacturing cost standpoint, but with no existing manufacturing in place is a questionable proposition given an unknown volume of sales. The latter makes a lot more sense from a manufacturing infrastructure sense, but as @bit_user pointed out earlier price of entry is $600. Even with less connectivity the chances of motherboard partners being interested in reducing costs of said platform is very low.

Turns out I was mistaken and the M1 Ultra is using an external interconnect rather than being a single piece of silicon as I seem to recall. The in silicon interconnect would be a simple matter of fusing off and then slicing. They have been doing both for decades now. Although, the addition of slicing thru circuitry could complicate things. Though it is still possible to make the design in a way that the connection between the two is added to a near final wafer if it has low enough defects so they can cut the consumer IODs without the connection even being there.

It would actually be two IGPs going unused unless display output was added to HEDT that didn't used to be there. It would also probably require a custom socket to enable one or both to be enabled. This is a valid point of concern, but still less wasted silicon than using an IOD capable of 12 memory channels and 12 CCDs for just four of each.

Low volume platform because there is no reasonable entry point means margins need to be higher to make a return on R&D - something that would be solved with 12 and 16 core models.

I'm just going to suggest you show us an example, in recent history, where anyone has actually done this. If you can't find such an example where a die could literally be cut in half, how can you be sure it's even feasible or worthwhile?


I just want to point out that Zen/Zen+ could go directly from one CCD to another. Not CCD -> IOD -> IOD -> CCD. The penalty (and thus viability) of a NUMA implementation has a lot to do with such particulars.


I think they just don't see a market for it. It's not as if the price would make it non-viable, or else the EPYC 9015 (list price: $527) could not exist. In fact, you could get a 16-core Zen 5 EPYC for $726 (9115) or $1214 (9135), depending on your clock speed & TDP requirements.

And with that, I'm out.

While researching, found out I remembered incorrectly regarding the Apple Ultra silicon as they apparently do use a bridge. While I still believe this is possible, it could require fusing off the link on both sides and that could add a not insignificant cost at such a scale or simply not be possible at the volume required. And honestly, even if it did require a small embedded silicon bridge - that's still got to be cheaper than using a whole freaking Epyc IOD.

This is true though this would still be less distance than the top right CCD of an Epyc/Threadripper to the bottom left CCD so I don't believe it would be as big of a problem as you think.

I think it is more likely that they do not want supply the market with 12 and 16 core non Pro Threadrippers. Perhaps AMD does not believe they can supply the demand. Perhaps the bean counters think that they will make more profit from the few people that cave and buy 24 core parts instead of seeking a more reasonable solution than selling dual CCD parts.

I suppose it could also simply just be that AMD does not want to eat into their consumer desktop 12c/16c sales by offering HEDT core count on the superior HEDT platform.