3D stacking is not necessary to add more cache to a CPU. Server chips have had more cache than mainstream CPU's forever without stacking it above the die. The fact that AMD and Intel haven't added more cache without stacking which would be cheaper than stacking just drives home the lack of cost advantage point even further.
A cursory look at older Xeon processors (around 2005) tells me that if server chips did have more cache than mainstream CPUs, it wasn't much (maybe 2x at best). And if we're going outside of x86, like say to POWER, L3 cache was typically off-die at the time.
Cache also takes up a large chunk of real-estate on the die:
(note L2 cache is the top left block in each core)
Assuming this is a Skylake based CPU, say an i7-6700(K) which has 8MB of L3 cache, L3 is already taking up 15% of the die space. Ballooning this up to say 80MB, would make L3 cache be at least as big as the processor itself, which isn't practical using a planar, monolithic technique.
In any case, the context to my answer is addressing the concern of given a choice between adding more cache (now that there's technology to add more without the issue above), or pushing out a new architecture to compete with what Intel's offering, it's cheaper to add more cache because you don't have to design anything except the infrastructure to support more cache. And if all AMD has to do to compete with Adler Lake now is add more cache, then they can do that to buy more time to make sure Zen 4 is ready to hit the ground running.
EDIT: If you want more die shots showing just how much space cache takes up:
Zen 3:
https://wccftech.com/amd-ryzen-5000...gh-res-die-shots-close-ups-pictured-detailed/ (L3 cache is taking up basically half a CCX chiplet's die area)
Penryn (Core 2 Duo 45nm):
https://en.wikichip.org/wiki/intel/microarchitectures/penryn_(client) (also, the L2 cache basically takes up a third to half the die area)
Nehalem:
https://www.anandtech.com/show/2658 (L3 takes up less space than the others, but still a significant amount)