AMD Explains Advantages of High Density (Thin) Libraries

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wiyosaya

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In some respects, this sounds like the programmable gate array concept. It is interesting to see this adapted to non-programmable chip design.

I am somewhat surprised, though, that this implies that such optimization was never before computerized. I would be really surprised if there were no computer optimization of chip layouts before this.

So, is this just AMDs marketing engine at the helm again?
 

Ragnar-Kon

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So more logic in a smaller area. Basically what chip designers have been doing since ICs were first invented. Nothing new...

[strike]EDIT: My bad, more logic in a smaller area without a die shrink. So essentially just housecleaning on current libraries. Still clever marketing.[/strike]
It is a die shrink, myyyy baaddddd. Doesn't seem anything like the 3-D transistors used in Intel's 22nm process though. Not that is necessarily a bad thing, I just thought it was similar to that originally.
 

ikefu

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Its also lower power consumption without a die shrink, which means more thermal headroom to up frequencies, add a die shrink on top of this and you suddenly gets LOTS more headroom.

So no, not just good marketing. But I am confused why this didn't happen already.

Doesn't fix their instruction per clock efficiency problem, but it will help increase CPU frequencies to cover for it while they work on that problem.
 

Shin-san

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Okay, what about the performance?!
[citation][nom]ikefu[/nom]Its also lower power consumption without a die shrink, which means more thermal headroom to up frequencies, add a die shrink on top of this and you suddenly gets LOTS more headroom.So no, not just good marketing. But I am confused why this didn't happen already.Doesn't fix their instruction per clock efficiency problem, but it will help increase CPU frequencies to cover for it while they work on that problem.[/citation]
I'm thinking that they are going for raw clocks.
 

acadia11

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[citation][nom]Ragnar-Kon[/nom]So more logic in a smaller area. Basically what chip designers have been doing since ICs were first invented. Nothing new... move along.But yeah... marketing at its finest (or worst?).EDIT: My bad, more logic in a smaller area without a die shrink. So essentially just housecleaning on current libraries. Still clever marketing.[/citation]

I thought it was going to be used in asphalt paver?

Ok , I just made that name up there is no chip asphalt paver.
 

dusk007

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I don't get that AMD focus on raw high clocks anyway.
Todays CPUs are constrained by heat and power anyway before the maximum clock is hit.
That is like building an aircraft turbine that can work well at Mach 2 while the entire airframe and efficiency requirements and noise regulations won't let the plane past 950 km/h anyway.
 

cjl

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Actually, if you believe Anandtech at least, this change reduces the maximum frequency that the circuit is capable of running, but it improves power consumption and die size. So, if anything, this is a transition away from the maximum frequency approach, and towards a more power-efficient design.
 

fazers_on_stun

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Seems like the new layout with the dense libraries reduces superfluous transistor counts, so that would reduce the power consumption and reduce the die size. So yeah I imagine higher clocks at the same TDP as BD, or lower TDP at the same clocks. IIRC BD originally was stated (by AMD's idiot marketing dept :p) to have 2 BN transistors, and then a couple months later that was reduced to 1.4BN when the actual engineers who designed it corrected the marketing dept's misstatement.

Anyway, I wonder if this is still 32nm - article didn't mention that. If Steamroller (due out in 2H2013?) or even later with Excavator (2014?), then it seems GF is not making progress with 22nm as quickly as they said previously..
 
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