I thought of this at first but then thought, no way, that would be a mess. Because then there would be an IO chiplet for the high-end, mid-range, and low-end. Or maybe it's only on the high-end and might make more sense?
But I'm betting there will be a design where you get something like a 256-bit interface to GDDR6 from a single chip, with a big Infinity Fabric link to another chip. Or maybe 192-bit with a 128-bit wide interface to be used for interchip communications? I don't know, I suppose it depends on how far they scale. Will this be just a dual-chip solution, or will it scale up to three or four chips? MI250X and the images of MI300 make me think it will be up to 4-way, with each chip having some local memory and a wide link or two to another chip.