What is your take on AMDs 90nm cache size factor and how far can AMD go in your opinion, with their current technology?
Hmm, I probably need to be careful with my tone to avoid antagonizing people further. The questions you ask are the million dollar questions of course.
I regards to cache sizes, I've made these comments many times before, but sadly I can never find the previous threads where I made them. In any case, larger L2 cache sizes really don't benefit the K8 architecture because of how AMD designed it. The K8 uses an exclusive architecture which means that the data in the L1 cache isn't duplicated in the L2 cache. As I understand it, this was more critical before because it offered the flexibility that the L2 cache did not need to be larger than the L1 cache and could be any size and it increase the total cache size since the 2 can be added together.
The other method of course is inclusive cache which Intel uses, which duplicates the L1 cache in the L2. In an exclusive cache, when an L2 cache line is copied into the L1 cache, an existing line in the L1 cache needs to be copied out into the L2 cache to make run for it. This of course adds latency and as a point of detail a victim buffer is used to increase performance. In an inclusive cache, when an L2 cache line is moved into the L1 cache, an existing L1 cache line doesn't need to be written to L2 because it is already duplicated there. This of course increases performance.
Since an exclusive cache puts more emphasis on the size on the L1 cache and less on the L2 cache, increasing the L2 cache size on an exclusive architecture doesn't increase performance as much as an inclusive cache. Even disregarding process differences, the reason why AMD doesn't have large L2 caches is, because they generally don't see as much benefits. Intel of course uses large L2 caches not only to reduce being bandwidth starved, but because they architecture benefits more. The thing that Intel needs to worry about with the inclusive cache is that they have the correct ratios between the L1 cache size and the L2 cache size. Since the L1 cache is copied to the L2 cache, the L2 needs to be a sufficient size to be of any use. Intel of course messed this up with the 128KB L2 cache in the Northwood Celerons, which was far too small and crippled their performance. The current 256KB Prescett Celeron Ds perform much better in comparison despite the pipeline increase.
As to how much cache you really need, there's of course a point of dimishing returns. The 1MB L2 cache per core in the K8 should be sufficient for desktop usage although AMD could use a shared cache in order to avoid duplication and maximize cache space. I suppose if AMD doesn't move to a shared cache, doubling the L2 could beneficial to hide any latency associated with the move to DDR2 although as you move to DDR2 800 and beyond the concerns really aren't there anymore. On desktops, I'm not sure if an L3 cache would be beneficial since with an OMC, the latency to the RAM is already low so if the L3 has higher latency than the L2 the benefit becomes increasingly moot. Servers of course love larger amounts of L2 and L3 cache so it would be useful there.
When you say how far can AMD go with their current technology I'm assuming you mean their 90nm process. They appear to be introducing some form of FD-SOI into their Socket F chips so they will be stretching the process a little further. I still think the big gains will come with 65nm. They've actually been tweeking their designs with the L2 cache in the new AM2's actually taking up less space on the same 90nm process than on the S939s. Revisions and advancements in the SOI process will obviously bring power and heat lower. However, that doesn't address the cost issue. It can be argued that Intel's 65nm process may not be advanced as AMD's 90nm SOI process, but it's still cheaper for Intel to produce. As long as AMD remains on 90nm they will be hampered in how they price their products. AMD may be able to produce a quad core on 90nm with the right thermals, but the size will make it problematic.
On the current 90nm process, I really don't see AMD increasing cache sizes, at least not in the desktop or mobile market since that's not really necessary or cost-effective. It should be noted that the Turion X2s that will be released all have 512KB of L2 cache per core rather than 1MB. With the FX-62 clocking in at 2.8GHz coming in June, AMD could probably sustain 1 more clock ramp to 3GHz, but after that it'll be next year and hopefully 65nm.
Will AMD be able to beat Conroe when it launches? Personally, I don't see it as very likely. Intel's new architecture appears superior to the K8 on a per clock basis which means Intel will probably have the lead in H2 2006. Improvements in AMD's process might shrink the gap, but I haven't seen evidence of their newer processes yet. Afterall, the TDP of the FX has actually increased and now the Opteron HE TDP has increased as well to 68W. AMD did say they would eventually have an Opteron EE version at 55W, but with Socket F already launching in H2, eventually will no doubt put it into 2007 and 65nm.
http://www.theinquirer.net/?article=30349
Interestingly, AMD has said that Socket F will use the exact same process as current Opterons and not FD-SOI as originally thought.
http://www.itjungle.com/breaking/bn031506-story01.html
First of all, these processors, which are due in the third quarter of this year, not the middle of the year, are based on the same 90 nanometer process that the current Opterons use.
In any case, AMD will certainly come out kicking in 2007 when their new K8L architecture comes out along with 65nm.
This is just my opinion of course, and I'm sure many people will disagree, but you asked for it. I'm sure MadModMike will say this is just google information, which I'm sure you can find there if you wanted.
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