AMD New Horizon Event - Breaking News

s1mon7

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Oct 3, 2018
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"Zen 2 will provide up to 2X the compute power per node, improved execution pipeline, doubled core density, and use half the energy per operation. AMD has doubled floating point performance with the Zen 2 microarchitecture. "


.....!
 

jimmysmitty

Champion
Moderator


Hype is never good.



It seems too good to be true for a die shrink. I can see double the cores doubling performance but halving the energy use while increasing cores? Seems too good to be true.
 

s1mon7

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Oct 3, 2018
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"Half the energy per operation" (not per chip). The way I read it is "at the same frequency, now you can fully load twice as many cores as before at the same power ", or "double the number of instructions the core is capable of computing at the same power". The end result is probably a chip with double the cores AND increased processing performance per core to some extent at power per core lower to some extent, where you can in total compute twice as much per Watt, even if the complete chip would use more power than a last-gen chip with half as many cores.
The 14nm->7nm die shrink can do that, with the architecture and IPC improvements filling the gaps of the wider architecture.

Or at least that's what they just claimed, and if their claims are even remotely close to being true, that's probably the most exciting thing in the semiconductor industry since the Core architecture debuted in 2006, if not bigger.

What I also understood to be confirmed, is that we will have 8 cores per CCX. That's prospects of 8-core mainstream chips with no interconnect. That would mean we would have separate dies for <8-core chips from the get-go, and interconnect used only on Threadripper-class chips, and that would be really darn perfect.
 

Giroro

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Jan 22, 2015
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It's halving the energy -per instruction-. That metric wouldn't increase with the number of cores, because an instruction will only execute on one core. So they calculate it using the maths.
Also, the CPU probably has some amount of fixed overhead that will get divided by the number of cores in order to calculate the energy per instruction so I could see at least one way where increasing the number of cores could improve efficiency overall.

So if there's two processors with the same power draw, but one manages to double the number of identical cores within that envelope, then the amount of power per instruction will be halved in the processor with double cores (because it is performing twice as many instructions).
Which is still really good for a process shrink. If I remember correctly, the 28nm to 14nm shrink only improved efficiency by about 30% instead of the 50% AMD is claiming for 14nm to 7nm.

 

jimmysmitty

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Thats sort of what I am getting at. No process shrink has been that efficient, at least that I have ever seen.

I will wait for third party benchmarks and metrics before I judge but to see a 50% reduction in power draw, or to say putting 2x the cores in the same thermal envelope, seems to be a pretty big leap for a single die shrink.
 

Ilya__

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Jan 7, 2016
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7nm and architectural improvements? I'm impressed. It was a long time coming, but then again 'Rome' wasn't built in one day ;)
 

s1mon7

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Oct 3, 2018
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Per Anandtech, TSMC officially claimed that their 7nm process offers a 60% power reduction and 70% area reduction from their 16nm FF process. This would be in line with that claim, even allowing some leeway for frequency increases, especially since the architecture was also improved, most likely offering at least some efficiency gains. Yeah, that would be insane. Yeah, I'm also waiting for the final product, but I can't hide my excitement. That's a ginormous leap.
 

Dantte

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Jul 15, 2011
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AWESOME!!!! Good for them, we need AMD to step it up and give Intel some real competition. Now, hopefully they can give Nvidia a run for their money too.
 

InvalidError

Titan
Moderator
Going with MCM chipset and chiplets now? Seeing how much of the Zeppelin die (around 1/3) was dedicated to IF and IO, I'm not surprised AMD decided to move most of that application-specific overhead off-CPU on 7nm so it doesn't have to be included in countless CPUs where it cannot be used for anything.

This should be interesting for the server and HPC markets.
 
Nov 6, 2018
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The only issue is how do you keep it cool. Man I suppose that's been a age long issue for AMD, competition is a very good thing in the tech world. A very good thing!
 

junglist724

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Apr 10, 2017
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The infinity fabric interconnect makes up a pretty large chunk of the power consumed on threadripper and epyc right now(25% of power consumption on a fully loaded 2990wx). I'm sure the central io die is more power efficient than having individual fabric links between 4 dies.
 

shrapnel_indie

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Jan 21, 2010
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Time will tell how good of a performance boost will be present. Intel is already nervous as it is... they need to keep on their toes, and AMD needs to keep them on them. (It shows how nervous Intel is with the stunts they've pulled along with the timing of them. Note though that nervous and knocked down to a lower position can be two different things... it remains to be seen how different they are with with Zen 2 (RyZen 3xxx series) though.)
 

shrapnel_indie

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Jan 21, 2010
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The loss won't be as large as it was with an external North Bridge... Considering its location, yes, it probably won't be as fast as it was, but it still should be much faster than located on the motherboard. We'l have to wait for benchmarks to see if it does hurt more than help.
 

InvalidError

Titan
Moderator

Having connections between core clusters go through an external IO between multiple dies consumes considerably more power than keeping the links on-die since you have orders of magnitude more parasitic capacitance to deal with than the much smaller and shorter on-die traces. If AMD is still using Infinity Fabric within the MCM chipset to provision chiplet ports, then all of the power overhead of managing the fabric is still there, just migrated from the CPUs to the chipset, so most of that power is still there as well. For AMD to make latency more even across chiplets though, it probably flattened the topology a bit.
 
Nov 6, 2018
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AMD crushes Intel again. The only thing that's keeping Intel alive is the never ending lies from America's Intel friendly "tech press".
 

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