AMD Piledriver FPUs

[BuckyJunior]

Hi, everyone. I know AMD FX Series CPUs have four modules, each containing two cores, which equals eight cores in total. How would all eight cores work at the same time when it only has four FPUs? Or does it just flip-flop between cores? What happens to the four cores that are inactive?

 

[dgingeri]

The FPU in those modules has 2 128bit pipelines, which must act together for 256bit AVX calculations. It is technically one FPU between the two, but can act like two kind of like Intel's HT.

 

[BuckyJunior]

So, both cores can still work at the same time per module? This is the first time I am really looking into this, so I'm a bit confused.

 

[dgingeri]

Yes, plus they can do out of order ops associated with just one core, if needed, while the other core is idle or is running integer instructions.

Figure it like this:
A McDonald's restaurant with 2 grills, 2 order stations at the drive through, two order takers, but just one ice cream machine with 2 nozzles. Either order station can use the ice cream machine to get cones for their orders, but they can only have one of them use it for banana splits (I know, McD's doesn't do banana splits, but bear with me.) and one order station could do 2 cones at the same time, if needed.

 

[BuckyJunior]

So, for tasks that require a lot of computing power (pipelines combine), both cores are combined, and for tasks that don't need as much computational power, (256 bit pipeline splits into 2 128 bit pipelines) the cores can work separately?

 

[dgingeri]

Yes, essentially. I don't know the specifics on how it works, but that's the information they've released.

None of it will really matter too much soon, as Ryzen is supposed to be released within the next 2-4 weeks. Then we're dealing with something all new. The FPU is supposedly similar in function to the Bulldozer line, in that it is 2 128bit pipelines that combine for 256bit calculations, and they can be addressed as 2 separate FPUs through their version of HT, but it supposedly performs better and there are 8 of them in an 8 core CPU. I've read that all of the Zen integer cores have 4 fully capable integer pipelines, too, so their version of HT should be much more efficient than Intel's. (Intel's 3 integer pipelines in SkyLake/KabyLake each have specialized use, so 2 calculations of the same instruction, such as a integer multiply or shift, can't happen at the same time with HT, and one of the instructions will get hit with 5-10 wait cycles, where Zen's HT should be able to do that simultaneously without the wait cycles.) We'll see soon enough, I think.

 

[BuckyJunior]

Yes, essentially. I don't know the specifics on how it works, but that's the information they've released.

None of it will really matter too much soon, as Ryzen is supposed to be released within the next 2-4 weeks. Then we're dealing with something all new. The FPU is supposedly similar in function to the Bulldozer line, in that it is 2 128bit pipelines that combine for 256bit calculations, and they can be addressed as 2 separate FPUs through their version of HT, but it supposedly performs better and there are 8 of them in an 8 core CPU. I've read that all of the Zen integer cores have 4 fully capable integer pipelines, too, so their version of HT should be much more efficient than Intel's. (Intel's 3 integer pipelines in SkyLake/KabyLake each have specialized use, so 2 calculations of the same instruction, such as a integer multiply or shift, can't happen at the same time with HT, and one of the instructions will get hit with 5-10 wait cycles, where Zen's HT should be able to do that simultaneously without the wait cycles.) We'll see soon enough, I think.

Thanks for the help! I'm going to wait for Zen anyways, but I just wanted to know how the architecture worked, as I have an FX-4300, and it's been good to me. I am a bit confused with the integer cores and all that, but I think I'll figure it out.