I suspect the actual amount of die space dedicated to ray tracing in RDNA 3 is relatively minor. Nvidia (and now Intel) have both RT hardware as well as matrix hardware, which does bloat things a bit more. Still, consider this: GA102 (used in RTX 3080/3090 series) measures 628mm square and has 84 SMs. It also has video codec stuff and other elements that are basically completely separate from the die size. Using
this actual die photograph, it's relatively easy to determine that of the total 628mm square die size, only 42–43% of that is used for the SMs. All 84 SM's thus use about 266mm square.
Each SM houses 128 FP32 cores, four tensor cores, and one RT core. The actual die size of an Ampere SM is around 3.2mm square. Based on die photos of earlier GPUs, I'd say only a relatively small amount of that area actually goes to the RT and tensor cores. Actually, I can do better than that on the estimate.
Here's a
die shot of TU106, and here's a
die shot of TU116. TU106 has RT cores and Tensor cores, TU116 does not. Using published die sizes and checking the area for just the SMs on those two GPUs, I got an SM size (on 12nm) of 5.5mm square for TU106 and 4.5mm square for TU116. There's also a
die shot of TU104 (but none on TU102), which gave an approximate size of 5.4mm square per SM. So, 5.4/5.5mm square per SM looks consistent and the entire SM is about 22% larger due to the inclusion of RT cores and Tensor core.
AMD doesn't have Tensor hardware, which means it's probably only ~10% more die area to add the Ray Accelerators. Best-case, then, AMD could improve shader counts and performance in rasterization by about 10–15% if it skipped all ray tracing support. Or put another way, certain complex calculations (those associated with ray tracing) run about ten times faster for a die space cost of 10%.