AMD SAYS IT CAN STILL BEAT INTEL CORES WITH OPTERONS

[9-inch]

http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears...

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

[/quote]These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect (hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.[/quote]

 

[Action_Man]

If only they could get you a new keyboard.

 

[Grimmy]

Well.. new keyboard MINUS a cap lock/shift button. :lol:

 

[leorick]

hmm... a keyboard with a comma key on the keypad would be nice :lol:

 

[MadModMike]

http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears...

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect

(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.

Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[linux_0]

http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears...

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect (hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.

AWESOME :-D

I'll take 2 please.

 

[TabrisDarkPeace]

.. With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.

Exactly which server makers are you referring to ?, as all the ones I've seen since 2003 have been offering 4 and 8 socket boards.
- HP / Compaq, Sun Microsystems, Iwill, Tyan, SuperMicro, and many others all are, and have been for ages.

Bear in mind the boards alone will cost US$500 - US$1000, just like they do now, and likely incorperate Serial Attached SCSI (SAS) supporting more than a home user will ever need.

As AMD use ccNUMA via HyperTransport they scaled ****ing well, far better than Xeons do past 4 processor cores. (The scaling was almost linear, and you can't get better than linear scaling).

The cache latency, from socket to socket (the worst cache scenario), due to the above (ccNUMA), was actually one of the lowest on the market.... well under 100 nanoseconds.

I can't figure out why the AMD fanboys here don't read the AMD websites:
http://multicore.amd.com - In particular has been running for ages, and explains it all fairly well.

Windows XP Pro, and Windows XP Pro x64 Edition, both support NUMA out of the box without modification btw.

If they implement L3 cache structure it'll either be:
- L3 cache per CPU socket
- L2 cache per CPU core

or something more along the lines of the L2/L3 layout some Sun UltraSPARC servers use:
- http://www.sun.com/servers/index.jsp
- Lots of reading on the Sun website regarding some rather smart 'cache structures' as you put it.
- If I recall correctly you want to 'compare' it to the 'boards' that the UltraSPARC IV / IV+ are being installed on for a 'rough' idea of how AMD might do it to get even better scalability than now.

However with 2 x boards, each with 4 x sockets, and 4 x cores per socket they'll get to 32 cores easily..... and most Operating Systems don't support more than 32 'processors'. So you want each of said processor (/core/SMT/CMT/HT/whatever/etc) to be giving the best damn performance it can give.

The problem is the interconnect between the '2 x boards', as all the processors on the same board can aggregate memory throughput to the sky. I mean an aggregate 25.6 GB/sec (moving to 51.2 GB, then over 96 GB/sec later on) basically 'is' a level 3 cache, but not when a CPU on board A tries to share / access memory that a CPU on board B is in control of. (Requires more expensive / advanced chipset than what I am using now )

eg: The Opteron 800 series can aggregate its own memory from its own memory controller and basically treat 3 other processors as 'northbridges' to the memory they are controlling. Using NUMA (WinXP, Linux, etc all support it) you can start hitting 20 GB/sec (on small reads including latency), and can sustain closer to 24+ GB/sec when streaming or performing reads of 128 bytes or more.

See: http://users.on.net/~darkpeace/forum_images/hit-a-brick-wall.png ; for a rough idea. (EDIT: Well... that was actually the CPU performance test in SANDRA, not memory after all.... but it kicked his systems ass - If anyone asks me, via PM, I'll run some more tests and post the results... otherwise I'll assume people have no real interest in the subject).

That image is of my own SANDRA results with the TomsHardware forums in the background on the very thread that asked for them, because someone didn't believe me.

==================================

Also have a look at the http://www.tyan.com website, the Opteron section in particular of course.

We've got HyperText and can link to public documents almost anywhere in the world, might aswell use it.

 

[apache_lives]

http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears...

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect

(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.

Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Woodcrest comes in at 2.93ghz, FBDIM and DIB will push it faster then the opterons for atleast 4 to 8way (a 2.66 can take on a A64, whats 2.93 going to do).

When intel gives us this type of hype we complain, but when were talkin AMD we dont - total BS - its just hype.

Besides - when Intel moves into the whole IMC and CSI (if there still usin csi) it will boost like the move to the K7->K8.

 

[apache_lives]

http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears...

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect

(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.

Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Oooo!! not to be a fanboy buy didnt you say that bout AMD desktop cpus?

 

[linux_0]

http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears...

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect

(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.

Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Woodcrest comes in at 2.93ghz, FBDIM and DIB will push it faster then the opterons for atleast 4 to 8way (a 2.66 can take on a A64, whats 2.93 going to do).

When intel gives us this type of hype we complain, but when were talkin AMD we dont - total BS - its just hype.

Besides - when Intel moves into the whole IMC and CSI (if there still usin csi) it will boost like the move to the K7->K8.


Any statements coming from Intel are gospell and statements from AMD are BS, we all know that right?

 

[MadModMike]

http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears...

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect

(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.

Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Woodcrest comes in at 2.93ghz, FBDIM and DIB will push it faster then the opterons for atleast 4 to 8way (a 2.66 can take on a A64, whats 2.93 going to do).

When intel gives us this type of hype we complain, but when were talkin AMD we dont - total BS - its just hype.

Besides - when Intel moves into the whole IMC and CSI (if there still usin csi) it will boost like the move to the K7->K8.

Whatever you say Apache... :roll:

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[49ers540]

MadModMike, don't stand too proud, Conroe is gonna smack you in your face. It will humble you

 

[pip_seeker]

It would be very interesting to see AMD make dual-core chips using the same 65 nanometer process, and get the power use way down below 50 watts. Some customers want the same performance and less heat, and still other customers will take even less performance for a lot less heat.

mmm now that would be lovely...

Intel's initial quad-core Xeon chips will actually be two dual-core chips sharing the same package (as it did to make the dual-core "Paxville" Xeons from single core "Irwindale" Xeons to blunt, however ineffectively, AMD's actual dual-core Opterons), but AMD will be doing real quad-core chips, putting four cores, probably with a per-core L2 cache and a shared L3 cache, on a single die.

Sorry, Intel fans... but which sounds like the better tech? Not that I'm a fan boy or anything. :roll:

 

[MadModMike]

MadModMike, don't stand too proud, Conroe is gonna smack you in your face. It will humble you

lol how is a piece of silicon gonna do anything but be my personal space heater? I'm sure Conroe is gonna smack me in the face...so I'll turn the other cheek and let AM2 smack Conroe 8O.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[cisco]

I would wait for the final release before you get too crazy. Have you forgot about the 4ghz P4 that was shown in 2003? I'm not saying Conroe won't be a good chip but wait until you have a mass produced chip to test, then you will know what you really have.

 

[linux_0]

I would wait for the final release before you get too crazy. Have you forgot about the 4ghz P4 that was shown in 2003? I'm not saying Conroe won't be a good chip but wait until you have a mass produced chip to test, then you will know what you really have.

:trophy: :trophy:

Indeed it is important to wait and see what happens.

Besides 65nm AMD CPUs are expected this year.

Trying to compare a 65nm Intel part against a 3+ year old 90nm part is INSANE.

 

[Legenic]

AMD probably will do better when going past 4 cpus because of hypertransport. intel will have to integrate the memory controller to compete that way.

lol how is a piece of silicon gonna do anything but be my personal space heater? I'm sure Conroe is gonna smack me in the face...so I'll turn the other cheek and let AM2 smack Conroe 8O.

you've read all the reviews and reports that say AM2 is about 3 - 5% faster than s939, right?

:trophy: :trophy:

Indeed it is important to wait and see what happens.

Besides 65nm AMD CPUs are expected this year.

Trying to compare a 65nm Intel part against a 3+ year old 90nm part is INSANE.

you're giving AMD too much credit. 3+ years old? like AMD hasn't made revisions and enhancements to their manufacturing process.

besides, you won't see big performance gains like the p4 did when they switch to 65nm. the p4 benefitted because of it's architecture. look at the pentium m, it didn't have any problems on 90nm, unlike the p4. AMD will be able to scale clocks higher and reduce heat, doubt performance will shoot through the roof.

 

[apache_lives]

AMD probably will do better when going past 4 cpus because of hypertransport. intel will have to integrate the memory controller to compete that way.



lol how is a piece of silicon gonna do anything but be my personal space heater? I'm sure Conroe is gonna smack me in the face...so I'll turn the other cheek and let AM2 smack Conroe 8O.

you've read all the reviews and reports that say AM2 is about 3 - 5% faster than s939, right?

:trophy: :trophy:

Indeed it is important to wait and see what happens.

Besides 65nm AMD CPUs are expected this year.

Trying to compare a 65nm Intel part against a 3+ year old 90nm part is INSANE.

you're giving AMD too much credit. 3+ years old? like AMD hasn't made revisions and enhancements to their manufacturing process.

besides, you won't see big performance gains like the p4 did when they switch to 65nm. the p4 benefitted because of it's architecture. look at the pentium m, it didn't have any problems on 90nm, unlike the p4. AMD will be able to scale clocks higher and reduce heat, doubt performance will shoot through the roof.

DIB made a dual socket P4 perform faster then the opterons at the time - intel 8 way and below will be quicker, the FSB isnt as slow as we expected - P4 was FSB hungry cause of its design, conroe etc isnt, and besides - who buys 16way servers - majority of the market isnt and when there going that high end they may as well go a diffrent brand chip for the purpose depending on needs ofcourse.

AMD 65nm THIS year? really?

Any statements coming from Intel are gospell and statements from AMD are BS, we all know that right?

- nope but AMD is BSing like intel does but no one complains bout AMDs BS.

And whats wrong with two dual core dies on one package? we've seen it on 65nm pentium d's - its a better idea then all in one package, also just cause AMD DOESNT USE IT - wait till they do. Its a great idea to get more high speeds.

If AMD does do quad core and with 90nm they will have a choice - slow warm chips, or slightly faster and hot chips - 90nm is at an end for them.

 

[Ycon]

AMD tries to tell us a lot of things >_>

 

[CompGeek]

No they aren't. AMD has shown the road maps and they'll arrive no sooner than 2007.
Opteron is the only contestor from the AMD side that i think will stay strong. The other's will get ripped apart(if they haven't already like the Poorion).

 

[pip_seeker]

AMD tries to tell us a lot of things >_>

and Intel completely lives up to all their hype everytime. :roll:

lol. :twisted:

 

[linux_0]

AMD probably will do better when going past 4 cpus because of hypertransport. intel will have to integrate the memory controller to compete that way.



lol how is a piece of silicon gonna do anything but be my personal space heater? I'm sure Conroe is gonna smack me in the face...so I'll turn the other cheek and let AM2 smack Conroe 8O.

you've read all the reviews and reports that say AM2 is about 3 - 5% faster than s939, right?

:trophy: :trophy:

Indeed it is important to wait and see what happens.

Besides 65nm AMD CPUs are expected this year.

Trying to compare a 65nm Intel part against a 3+ year old 90nm part is INSANE.

you're giving AMD too much credit. 3+ years old? like AMD hasn't made revisions and enhancements to their manufacturing process.

besides, you won't see big performance gains like the p4 did when they switch to 65nm. the p4 benefitted because of it's architecture. look at the pentium m, it didn't have any problems on 90nm, unlike the p4. AMD will be able to scale clocks higher and reduce heat, doubt performance will shoot through the roof.


The architecture is over 3 years old.

The performance gains Intel claims for their 65nm line are not impressive at all considering. If this is the best they can do they will be in trouble.

 

[Ycon]

And the point is?

And yes, with Conroe they will live up to the hype.

 

[linux_0]

And the point is?

And yes, with Conroe they will live up to the hype.

How do you know?

Do you have proof?

Manufacturers make claims all the time and rarely live up to them.

What is so special about the Conroe?

How much is Intel paying you???????????????

 

[CompGeek]

About Conroe
Well there are benchies, and other builds using similar technology that curently rock hard. No matter how you take it Conroe will beat AM2 clock per clock. By how much,well i predict somewhere around 15% .
About AM2
We do have a THG benchmark that is of course coursed with the mem. controller bug(or so you insist) but we also have a Inq. article stating that AM2 with DDR2 800 will bring a minor 3-5% improvement over AMD on 939 with DDR that certainly can be placed as a fact.

AM2 will launch 2 months earlier than Conroe.

Not to mention that the Conroe hype is also infecting AMD people. They have finally admited that they'll have some nasty competition.

BTW Poorion X2 will be on the shelves soon. I can't wait to see how poo or not poo it performs.