When a process tech says X% savings on power, what they mean is "At a given Mhz a single transistor will require (1-x%) * original voltage to flip a transistor."
So lets say it takes 1V to flip a transistor on the old node, and they claim a 30% savings. (1-.3 ) * 1V = 0.7V on the new node.
There's a certain minimum current that goes through each transistor flip state. As speed increases, it gets harder and harder to satisfy that current demand at a given voltage. So you ramp the voltages again to push the current. (Voltage = push. Current = how much at a time.) High current demands also lead to voltage sag, which makes it look like a voltage drop. (The voltage across a short circuit is 0) This is why we have things like load line calibration. As power = V * V / R, you start to get an exponential increase in power as you ramp voltages. Hence why you quickly get into thermal runaway with voltage overclocking.
Also smaller features allow smaller distances between structures, thus you don't have to worry about electron propagation (travel time) as much. This is one of the reasons you can ramp higher clock rates.
So you can have power savings, or increased clock rate, but not both without some trade off.