Chris, I believe it would help your readers a lot by elaborating on the significance of this announcement. For one, TR systems support a much larger number of PCIe lanes than the competition. And, by now the bandwidth limit imposed by Intel's DMI 3.0 link is very well documented. Although it has taken many years for hardware vendors to exploit the raw bandwidth of x16 slots for storage subsystems, the industry is now embracing that vast potential. For example, there is an obvious engineering elegance with 4 NVMe SSDs @ x4 PCIe 3.0 lanes = x16 edge connector. And, allowing modern RAID modes to span multiple add-in cards is another exciting development that clearly multiplies the raw upstream bandwidth. As such, there is now a realistic opportunity to assemble non-volatile solid-state mass storage with the same raw speed as common DDR3 DRAM! Those of us who were promoting this capability just 5 years ago were called dreamers. Just do the numbers: one x16 edge connector has a MAX HEADROOM of 15,753.6 MB/second, and twice that with two x16 edge connectors -- truly exciting!
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