News AMD Zen 5 support arrives with five new instructions — GNU compiler collection posted

[Admin]

Per an update to GCC, Zen 5 will apparently have support for new instructions, including the AI-focused AVXVNNI.

AMD Zen 5 support arrives with five new instructions — GNU compiler collection posted : Read more

 

[yeyibi]

AVX is unusable, because there is no standard. Each processor has different instructions.
New processors do not support older instructions. Even the same CPU doesn't support the same instructions on all cores. Is a hell.
The only thing that can be trusted to work is SSE4.2, which is almost 2 decades old, but is even supported in ARM and smartphones.

 

[Findecanor]

AVX is unusable, because there is no standard. Each processor has different instructions. [...]
Even the same CPU doesn't support the same instructions on all cores. Is a hell.

I think you are referring to AVX-512, for which that is more or less true.
It is because of that irregularity that Intel decided to renumber the sets as AVX10.

Intel issued a microcode update that disabled the AVX-512 instructions on the CPUs where all cores did not support it.

New processors do not support older instructions.

AVX is supposed to have been supported on new Intel and AMD CPUs since 2011. AVX2 since 2015.
Is there any of those instructions that doesn't work on some newer processor, or did you only refer to a subset of AVX-512?

The only thing that can be trusted to work is SSE4.2, which is almost 2 decades old, but is even supported in ARM and smartphones.

Do you mean to running intel code in emulation on ARM64?
Apple's Rosetta supports up to SSE4.2.
ARM does otherwise not run Intel instructions.

x86-64 code on Windows is supposed to use the CPUID instruction to check what is supported before it tries to use an instruction set extension. Mac OS has API calls for the same purpose.
Linux distributions have instead standardised on four "Microarchitecture levels" to compile against so that code wouldn't have to.

 

[bit_user]

AVX is unusable, because there is no standard. Each processor has different instructions.

As @Findecanor said, you presumably mean AVX-512. In that case, the common baseline is basically what Skylake-X had. In the Linux universe, they blessed that as level 4 of the x86-64 ISA pyramid, so to speak, making it a fairly standard compilation target.

New processors do not support older instructions.

The AVX-512 instructions not implemented by newer CPUs are pretty much just some of those found in Xeon Phi, which was a specialty HPC product and thus not an issue for most software out there.

Even the same CPU doesn't support the same instructions on all cores. Is a hell.

That's actually not true. Intel never supported heterogeneous ISA, even though there were hacks to enable it in the early days after Alder Lake launched.

The only thing that can be trusted to work is SSE4.2, which is almost 2 decades old, but is even supported in ARM and smartphones.

First, AVX & AVX2 are trustworthy, in that any CPU which supports them will implement them fully and consistently. Their biggest issue is just that the E-cores prior to Gracemont (e.g. Jasper/Elkhart Lake, Gemini Lake, Apollo Lake, etc.) didn't support them.

Leaving that aside, SSE4.2 didn't ship until November 2008, which is 15.25 years ago - not really almost 2 decades.