News AMD's EPYC Milan-X is Official: 3D V-Cache Brings Up To 768MB of L3 Cache, 64 Cores

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Wait...

Epyc 7373X16/323.05 GHz3.8 GHz240 W768 MB

That looks TOO good to be true... 768MB of* cache for a single CCD config? Is that correct? If so, that's basically ThreadRipper 3D when it comes out :O

Regards.
 
Yuka said:
Wait...

Epyc 7373X16/323.05 GHz3.8 GHz240 W768 MB

That looks TOO good to be true... 768MB of* cache for a single CCD config? Is that correct? If so, that's basically ThreadRipper 3D when it comes out :O

Regards.
Click to expand...
No Milan processors are single CCD from what I can tell, they're either 4 or 8. In the case of the 7373X, it'd be 8 CCDs (2 cores enabled per CCD) with 96MB L3 per CCD.
 
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TJ Hooker said:
No Milan processors are single CCD from what I can tell, they're either 4 or 8. In the case of the 7373X, it'd be 8 CCDs (2 cores enabled per CCD) with 96MB L3 per CCD.
Click to expand...
As far as I remember, the CCDs are still 8 cores (1 CCX), so for the 16 core one, it'll be 2 enabled CCD instead of 8 (assuming 2 full CCDs and not some weird combination of them). So that way, the top end gets 8 CCDs with 8 cores each, making it 64 cores in total. That's why I find it weird the "L4" (they call it L3, but I'm not too sure) cache is the same for all, unless they put the L3 off-CCD? Or they keep the L4 in all CCDs, but with the cores disabled? 😵

Such a weird setup that would be, haha.

Regards.
 
Yes, it's crazy hellish lots of cache.
AMD is again striking down the memory access speed bottleneck that haunts modern extra-high-core-count CPUs. First strike was on the memory controllers when the first multicore CPUs bottlenecked on them.
This would require saned size TLBs and more page table accessors to keep up with the increased load though (naturally, when you access more memory in the same timespan, you need larger TLBs to avoid bottlenecking at page translation phase), I wonder if and how they'll manage to fit this all in already tight thermal budget.
Also, on a side note, growing up caches this high means there are no good expectations for DDR5 evolution.
For practical purpose, having that much of cache means virtualized OS kernels most juicy bits will almost always reside in caches, that can't be a bad thing.
 
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gg83 said:
I was under the impression that more cache equals a lot more energy required. I didn't see any mention about energy usage.
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A bit, yes, but not that bad for L3 caches (compared to L1/L2). For L3 caches, increasing amounts worst concern equals to raw physical space occupied which is also limited, and so here they go with the 3D stacking.
 
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Yuka said:
As far as I remember, the CCDs are still 8 cores (1 CCX), so for the 16 core one, it'll be 2 enabled CCD instead of 8 (assuming 2 full CCDs and not some weird combination of them). So that way, the top end gets 8 CCDs with 8 cores each, making it 64 cores in total. That's why I find it weird the "L4" (they call it L3, but I'm not too sure) cache is the same for all, unless they put the L3 off-CCD? Or they keep the L4 in all CCDs, but with the cores disabled? 😵

Such a weird setup that would be, haha.

Regards.
Click to expand...
Milan CCDs have 8 physical cores on the die/per CCX, but that doesn't necessarily mean 8 cores enabled. They can have as little as one core enabled per CCD/CCX, as is the case for the 72F3.
https://www.anandtech.com/show/16529/amd-epyc-milan-review/2
At the bottom is AMD’s sole 8-core offering, meaning only 1 core per chiplet
Click to expand...

The reason all the processors listed have 768 MB of cache is that they all have 8 active CCDs (with 96MB of L3 per CCD, 32MB on the CCD itself + 64MB of 3D V-cache). They just have varying numbers of cores enabled per CCD.
 
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TJ Hooker said:
Milan CCDs have 8 physical cores on the die/per CCX, that doesn't necessarily mean 8 cores enabled. They can have as little as one core enabled per CCD/CCX, as is the case for the 72F3.
https://www.anandtech.com/show/16529/amd-epyc-milan-review/2


The reason all the processors listed have 768 MB of cache is that they all have 8 active CCDs (with 96MB of L3 per CCD, 32MB on the CCD itself + 64MB of 3D V-cache). They just have varying numbers of cores enabled per CCD.
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Holy cow; I missed that.

Interesting then! So there's a good chance the plebeian desktop parts with 3D cache will be 192MB total L3 (I'm pretty sure it's L4 >_>) for all SKUs if we're lucky XD

Then again, they could segment the market even more like that... A 6c/12t with 96MB and another 6c/12t with 192MB; that would be hella interesting.

Regards,
 
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Makaveli said:
There is no information from this article on desktop ryzen so why both asking for it?

Its clearly talking about Enterprise products.
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Roger that. But since I'm not an Enterprise, what's of interest are these revelation's implications wrt PC cpus.
 
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lazyabum said:
Forget it, Consumers come in dead last over anything AMD, Take graphics cards for example.
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Its all about following the money. Both intel and AMD make more money from enterprise products that is their bread and butter. If one is stuck in the consumer mindset where you think desktop cpu and gpu's is what drives them...then still alot to learn about both of these companies.

All of their enterprise products will always take priority over consumer parts.
 
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gg83 said:
I was under the impression that more cache equals a lot more energy required. I didn't see any mention about energy usage.
Click to expand...

This is true but the 3D stacked SRAM should be really good on energy efieceny. Since its a separate chip they are using TSMC's SRAM optimized libraries to make the chip. I doubt in a server chip that the extra energy/heat from the SRAM used for the l3 cache is a major factor.
 
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SeQUOTE="TJ Hooker, post: 22509885, member: 1470815"]
No Milan processors are single CCD from what I can tell, they're either 4 or 8. In the case of the 7373X, it'd be 8 CCDs (2 cores enabled per CCD) with 96MB L3 per CCD.
[/QUOTE]

Yes correct. AMD currently offers 16 core 256mb cache as well.

These cpus are clocked higher so they are targeted for customers who needs huge cache and fast cores but do not benefit from more cores.
 
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