This is the first place I've read about Zen4 using 4cores per CCX, so back to two CCX'es per CCD, which would mean L3 is now only available to 4 cores at a time instead* of 8. I wonder if that change was due to the increase in L2 in order to compensate for latency? Hm... The other alternative is they're betting on VCache to increase the L3 for the CCX'es anyway, so they're not bothered by the split anymore? Interesting things you can read between the lines.
Anyway, making 4 cores per CCX does have the direct benefit of being able to power the groups with a bit more granularity, which can have positive effects in power consumption.
Other than that... I was expecting the IF to be clocked higher, but making it 3Ghz means it'll be able to run DDR5-6K 1:1, so maybe the sweet spot for Zen4 will be between DDR5-5200 and 6000? That is actually not bad at all.
I wish we could see a proper uArch diagram for it... I can't find any for Zen4 8(