Question Anyone know what the cache on the 3950x will be?

Eximo

Titan
Herald
Not sure about SSDs, but I imagine they exclusively communicate to each other using the infinity fabric / memory bus. Wouldn't make a huge amount of sense to have cache running at such a low speed.

Now how it works on each chiplet could be completely different and they might all share the L3 cache.

I'm not seeing any block diagrams that go into that detail.
 
Jun 30, 2019
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Yeah same. I'm guessing since only some basic specs and benchmarks have been released, and especially since the benchmarks may even be using pre-product silicon, block diagrams don't exist yet.
 

Eximo

Titan
Herald
Pre-production silicon is usually the same architecturally, lower clock speeds and the like. They make it more for testing the output of the manufacturing process and to gauge yields. As well as to work on drivers, board, and OS compatibility.

I can't imagine them making any drastic changes this deep into a product design. Would require a lot of re-work.

I struggled to find any diagrams for TR2 that went down to the cache level. Usually just showing their marketing material for PCIe lanes, how the memory bus works, and other chip based stuff.

Ryzen CPU diagrams might actually be more forthcoming in that regard, but I don't know how they would have scaled it up, if at all.
 
Jun 30, 2019
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Interesting. So theres more cache total but now the speed of its lower due to higher latency and less l1. Does That help or hurt performamce? Ive only built one pc and still have a lot to learn about this stuff.
 

TJ Hooker

Glorious
Herald
There are so many factors that affect modern CPU performance, trying to predict the performance impact of the cache redesign in particular would be very difficult. It would also likely vary based on workload. I can only assume that it provides a net benefit, otherwise I don't know why AMD would have done it.

To see actual performance your best bet is to look at relevant benchmarks.
 

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