Soooooo! Let me get this right, rather than ARM keeping true to their Usual RISC formula of hardwairing all this complexity, they are now adding to the Instructions that access the cores. That would mean that the Kernel (like in windows) now has control of how the CPU routing is organised and brings all the overheads and latency with it.
The RISC architectures were ment to be Hardware Driven and routed so that its concepts didn't need to add to the Basic ISA. With these changes we are adding to the ISA to access certain elements of the core meaning that is is becoming CISC by definition.
So, in other words, the new management running ARM are now cutting the corners of the rules. Or their Engineers are not good enough to create the Sequential logic control to reroute this functionality as Native (true RISC).
The Mesh design could have been made as a round robin style core based PIPELINE, where each core is controlled by a central core (like with the old Cell architecture) and Pipeline the instructions to various cores, then collecting the response from the other end. There problem thus becomes that the traditional PIPELINE model would become massively more complex. You can only have one or the other. Only when they decide to restructure the ISA and reduce the amount of clock cycles per instruction, will they ever be able to reduce the latency, to effectively be able to make a Multicore work effectively as a co processor. Current ISA takes 4-6 steps to pass through a Instruction decode, and more steps on the accumulator to complete and free up the accumulator for next instruction. But SMT or its equivalent would need to be removed.
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