News Arrow Lake die shot shows off the details of Intel's chiplet-based design

[Admin]

Die shots of an Arrow Lake desktop CPU have been published online, revealing the inner design changes Intel has made to Arrow Lake, including its all-new chiplet (tile)-based design and improvements to the cache design.

Arrow Lake die shot shows off the details of Intel's chiplet-based design : Read more

 

[bit_user]

The compute die is fabbed on TSMC’s bleeding-edge N3B node,

No, it wasn't bleeding edge. Apple was already shipping M3-series SoCs on it for like 8 or 10 months, by the time it launched and was in the process of finalizing the M4-series on N3E. Intel's own Lunar Lake launched on N3B, months earlier.

Intel’s first attempt at a desktop chiplet-based competitor has not been well received

It's not their first attempt. That was Meteor Lake-S, which they cancelled. There are even Meteor Lake-S engineering samples floating around, proving that they got quite far before pulling the plug on it.

The distinction isn't mere nit-picking. It means that, while they were finishing Arrow Lake, they already had an idea of what issues and challenges they would face. Maybe it was still too late to do much about them, but that's different than going in completely blind.

and 3MB of L2 cache per E-core cluster, with 1.5MB shared between two cores directly.

First, each E-core cluster has 4 MB of L2 cache. Aaron obviously just glanced at the image (missing the 1 MB slice, in the process) and not the actual specs. Otherwise, wouldn't have made that error.

Second, nowhere does the original author (High Yield) ever say that the 1.5 MB slices are specifically shared between the two E-cores on either side of them. If Aaron just took a wild guess that's what was happening, he really shouldn't do that.

I'll do you a favor and link exactly the part of the vid where the author talks about the E-cores, so you can see/hear for yourself. It's pretty short (only about 16 seconds), at 13:04.

View: https://youtu.be/wusyYscQi0o?t=784
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Better yet, I found some evidence that the E-cores don't have preferential access to the 1.0 or 1.5 MB L2 slices adjacent to them. If they did, then there should be a corresponding bump in this graph. Instead, it's flat all the way out to 4096 kiB:

Source: https://chipsandcheese.com/p/skymont-in-desktop-form-atom-unleashed
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It's also kinda weird that Aaron only linked to Andres' tweet, which was nothing more than a couple frame grabs from that Youtube video and a link to the youtuber's account. He could've just linked straight to the video and included his own frame grabs of it.

Tagging @PaulAlcorn and @JarredWaltonGPU . I hope we can see better fact-checking, in the future.

 

[DS426]

Kind of late to build hype and excitement for Arrow Lake now. 🤣

 

[bit_user]

Kind of late to build hype and excitement for Arrow Lake now. 🤣

Yeah, I've seen die shots of it that came out, before. I haven't gone back and tried to compare them, but I know it's not easy to make these photos and I think the more the merrier!
: D

I think I read they have to actually run the de-lidded CPU and use an infrared sensor, or else you wouldn't see much.

Edit: here, I found them.

https://www.tomshardware.com/pc-com...ions-break-down-intels-disaggregated-approach
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[DS426]

Yeah, I've seen die shots of it that came out, before. I haven't gone back and tried to compare them, but I know it's not easy to ...

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My silliness aside, I agree: the more, the merrier! Indeed it sounds like it's quite hard to get good die shots.

 

[Eximo]

LGA 1366 the last time they did a one and done socket/chipset?

I think LGA 775/771 had some life in it beyond the consumer chips.

 

[usertests]

All Intel desktop CPUs for the foreseeable future are going to be made of chiplets like this. Hopefully they can make some of their own next time.

Is it just me, or does that Media Engine look huge? Isn't that what's handling video decode/encode?

 

[oninoshiko]

Who would ever buy a glued together chip!? /s

 

[usertests]

Who would ever buy a glued together chip!? /s

Someone looking for power efficiency, somehow. Arrow Lake is said to be more efficient than Raptor Lake at lower TDPs.

 

[Thunder64]

Someone looking for power efficiency, somehow. Arrow Lake is said to be more efficient than Raptor Lake at lower TDPs.

You missed the joke. Years ago Intel said AMD was essentially inferior for using "glue". I guess this was during the Zen 2 days.

 

[usertests]

You missed the joke. Years ago Intel said AMD was essentially inferior for using "glue". I guess this was during the Zen 2 days.

I already hit Like for the joke.

Sniffing the glue is obviously the root cause of the latency problems, and overall performance loss is from using less aggressive voltages than Raptor Lake.

 

[endocine]

looking at this from the perspective of a rear view mirror, this die shot appears to show a bunch of dies 'glued together' with re-purposed desktop parts, a poor track record and lack of ecosystem.

 

[Mr Majestyk]

I already hit Like for the joke.

Sniffing the glue is obviously the root cause of the latency problems, and overall performance loss is from using less aggressive voltages than Raptor Lake.

More like memory controller is not on the cpu tile (will change with Panther Lake), ringbus is much lower clocked because this was the root of most problems with Raptor Lake, pushed beyond breaking point to beat AMD in benchmarks cheered on by the tech sites.

 

[bit_user]

More like memory controller is not on the cpu tile (will change with Panther Lake), ringbus is much lower clocked

Eh, I hear this a lot, but I'm not sure it's so simple.

AMD has its memory controller on a different die and just compare its Infinity Fabric frequency to Arrow Lake's Ring & D2D. And yet, Ryzen 9000 still managed to solidly beat Arrow Lake on memory latency:

Source: https://chipsandcheese.com/p/analyzing-lion-coves-memory-subsystem
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That's 14.3 ns less, or about 16.8% faster.

According to this, the stock frequency of the 9950X's infinity fabric is only 1.8 GHz.

SkatterBencher #81: Ryzen 9 9950X Overclocked to 5900 MHz - SkatterBencher

We overclock the AMD Ryzen 9 9950X to 5900 MHz with the ASUS ROG Crosshair X670E Hero motherboard and EK water cooling.

skatterbencher.com

I think part of the problem is Intel's L3 architecture and the ring bus, itself. Intel allows a single core to utilize up to the entire L3 cache, while AMD wisely segments their L3. That fundamentally scales better.

 

[Lucky_SLS]

Just give us Bartlett lake, Intel 😴

 

[dalek1234]

"sight to behold under the hood."

Because when it comes to CPU's, it's the looks that matter the most. Nobody buys CPUs on performance anymore. 🤦‍♂️🤔

 

[bit_user]

Is it just me, or does that Media Engine look huge? Isn't that what's handling video decode/encode?

Arrow Lake has 2x media engines. Each has a separate encode and decode block. Intel's slides seem to imply that each engine has enough horsepower to encode 8k 10-bit HDR AV1 @ 120 fps, which is quite impressive. There is some ambiguity whether they support encoding all supported codecs at that rate, but they definitely say they can achieve that for at least some of the supported codecs.

Source: https://www.tomshardware.com/pc-com...tivity-and-power-efficiency-but-not-in-gaming
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Notable in its absence is VVC (H.266). I wonder if they planned to support that via subsequent software updates or maybe it just didn't make the cut.

 

[usertests]

Notable in its absence is VVC (H.266). I wonder if they planed to support that via subsequent software updates or maybe it just didn't make the cut.

https://en.wikipedia.org/wiki/Intel_Quick_Sync_Video#Development

They used the same one that is in Alchemist and Meteor Lake. Some parts of Meteor Lake were effectively dropped into Arrow Lake, including the NPU.