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[thestryker]

Keeping the architecture the same, but on bigger vs smaller nodes, the smaller nodes will clock higher at the same power, or clock the same at lower power.

Only as far as what the node is capable of in the first place.

Rocket Lake (Sunny Cove aka Ice Lake's architecture) clocked higher on 14nm than even Tiger Lake ever managed on 10SF.

 

[thestryker]

That's why I said it "could" increase performance. The question was how does better access to memory increase clock speeds?

The cache uses less power which is the improvement that enabled higher clocks. Nothing to do with the actual performance of the cache itself.

 

[helper800]

The cache uses less power which is the improvement that enabled higher clocks. Nothing to do with the actual performance of the cache itself.

So you are saying the memory access became more power efficient and they then dumped that power into the cores? If so, I understand what you are saying now, however, the way you presented that information is still incorrect to my understanding. The clocks did not get faster because of memory access improvements, they got faster because intel pumped the cores with more power. These statements are not equivalent to each other.

 

[bit_user]

I've seen zero evidence indicating they changed the node between ADL/RPL. If you've got some please share.

Really? I'm disappointed!
: D

"Intel introduced an enhanced version of the Intel 7 process in late 2022 with the introduction of the company's 13th Generation Core processors based on the Raptor Lake microarchitecture. Nicknamed "Intel 7 Ultra" internally, the new process is a full PDK update over the one used by Alder Lake, their 3rd generation SuperFin Transistor architecture. Intel says this process brings transistors with significantly better channel mobility. At the very high end of the V-F curve, the company says peak frequency is nearly 1 GHz higher now. The curve itself has been improved, shifting prior-generation frequencies by around 200 MHz at ISO-voltage, or alternatively, reducing the voltage by over 50 mV at ISO-frequency."

Source: https://en.wikichip.org/wiki/7_nm_lithography_process#Intel_7_Ultra
​

The cache redesign, which is absolutely part of the architecture, is actually what allowed for the higher peak frequencies.

I've seen zero evidence of this. If you've got some, please share!
; )

I think their cache enlargement was a consequence of a maturing Intel 7 node, and not a cause of anything other than higher resulting workload performance.

There's really no good argument to hold back your core clock speed, based on your L2 cache. L2 is both heavily and easily pipelined. Furthermore, its associativity went up from 10-way to 16-way, between Golden Cove and Raptor Cove (source: https://chipsandcheese.com/p/a-preview-of-raptor-lakes-improved-l2-caches ). That means the additional capacity was simply added by means of parallelism, not frequency.

 

[thestryker]

I've seen zero evidence of this. If you've got some, please share!
; )

Better missrate = less power consumption and you know where it came from 🤣

Really? I'm disappointed!

I actually never saw that somehow.

 

[bit_user]

Rocket Lake (Sunny Cove aka Ice Lake's architecture) clocked higher on 14nm than even Tiger Lake ever managed on 10SF.

That's much more a commentary on their 10 nm SF node than it is about Sunny Cove.

 

[helper800]

On the subject of CPU architectures, nodes, et cetera, I consider myself barely knowledgeable. I have just enough educational background in science, reading done over the years on architectures, and formal logic systems to be dangerous on the subject, so please take what I say with a helping of salt @thestryker

 

[bit_user]

The cache uses less power which is the improvement that enabled higher clocks. Nothing to do with the actual performance of the cache itself.

This is easily disproven by a W/GHz benchmark that operates purely in L1 cache. L2 only uses power when you have L1 misses. Sadly, I do not have a CPU with Raptor Cove cores, or else we could settle this matter.

It is a a big claim and not something you should make without a source of some kind. I'll be waiting...

 

[helper800]

Better missrate = less power consumption

Can you quantify the missrate efficiency uplift? The answer to that would be determinative of whether or not the power consumption efficiency increase was 0.1% of the CPUs total chip power budget or 1-3%

 

[TerryLaze]

Yeah, also requiring less power to do so, which adds more headroom for cranking up frequencies. This is why you tend to see the formulation of: "X performance at same power; Y power at same performance", when someone like TSMC introduces a new node. In this analysis, the constant is the microarchitecture, which is usually something like an old ARM core design that they fab on both nodes for comparison purposes.

Doesn't change the fact that there are high density libraries and high performance ones. AMD until now has been only high performance with them only now talking about using a hybrid approach, for servers, that will also use the higher density one.

You can't have everything in the same library, you either get high clocks or high performance, or you go for option 3 that has neither.

Three libraries tune speed and density on TSMC’s 3nm process – Tech Design Forum

The three libraries are intended to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and frequency.

www.techdesignforums.com

The three libraries for N3 are divided in HD, HC and HPC, with the HD being the one that is expected to offer around a 60 per cent improvement in density for designs compared to N5. HPC offers a significantly smaller scaling benefit but can support higher-frequency circuits. HC lies between the two, though with a higher weighting to density rather than speed gains.

Yes, mostly. One of the more interesting and recent case studies is Rocket Lake, where Intel backported the cores of Ice Lake from their 10 nm to their 14 nm node. The result was that it ran too hot.

It's like 88 compared to 87 of the previous gen....
Overclocking temps are not normal temps.
https://www.computerbase.de/artikel/prozessoren/intel-core-i9-11900k-i5-11600k-test.75538/seite-5

 

[bit_user]

On the subject of CPU architectures, nodes, et cetera, I consider myself barely knowledgeable.

None of us here is a CPU designer or even an EE. We're all sort of stumbling around in the twilight, together.
: )

I did once work in a firmware team for a custom chip with custom RISC cores. I picked up bits and pieces from the hardware guys, but I still can't claim to have any real expertise in the matter.

We used to have some EE's around here, but I haven't crossed paths with any, in a while. At least, not folks with deep experience in digital design.

 

[thestryker]

That's much more a commentary on their 10 nm SF node than it is about Sunny Cove.

Which is my point: newer, and better, node doesn't always mean higher clocks. I don't think 18A is going to be high clocking because it doesn't have the higher voltage scaling of their prior nodes. In practice it might only match the clocks of Intel 3 at best, but it'll be using less power to do so.

TSMC's N7 nodes are also an interesting look because they started DUV. The move from Zen 2 to Zen 3+ with clocks went from 4.4Ghz to 5Ghz across 2 architectures (and one power focused revision with a new memory controller) and 3 different node revisions, but Zen 3+ had lower maximum power. If you look at desktop it was 4.7Ghz to 4.9Ghz on the 16 core parts.

 

[bit_user]

Doesn't change the fact that there are high density libraries and high performance ones.
...
You can't have everything in the same library, you either get high clocks or high performance, or you go for option 3 that has neither.

Somewhere, I read something about one of TSMC newer nodes (maybe N2?) having a variety of cells that you can use, based on the needed current capacity (IIRC). I think it was exploiting a property of their GAA design that varied gate height, or something like that.

It's like 88 compared to 87 of the previous gen....

But, having larger die area, it should've been easier to cool.

The real tell is how much power it used, not temperatures.

 

[bit_user]

Which is my point: newer, and better, node doesn't always mean higher clocks.

It was a denser node and more efficient, but "better" depends on what you want to do with it.

 

[helper800]

Which is my point: newer, and better, node doesn't always mean higher clocks. I don't think 18A is going to be high clocking because it doesn't have the higher voltage scaling of their prior nodes. In practice it might only match the clocks of Intel 3 at best, but it'll be using less power to do so.

TSMC's N7 nodes are also an interesting look because they started DUV. The move from Zen 2 to Zen 3+ with clocks went from 4.4Ghz to 5Ghz across 2 architectures (and one power focused revision with a new memory controller) and 3 different node revisions, but Zen 3+ had lower maximum power. If you look at desktop it was 4.7Ghz to 4.9Ghz on the 16 core parts.

You can look at the W/Clock ratio and know that; smaller node = lower power or higher clocks. Just because clocks did not increase much that does now mean its W/Clock efficiency did not get better. When it comes to clocks that are higher or power that is lower, the main determining factor seems to be the process node as the main determinative factor.

 

[thestryker]

On the subject of CPU architectures, nodes, et cetera, I consider myself barely knowledgeable. I have just enough educational background in science, reading done over the years on architectures, and formal logic systems to be dangerous on the subject, so please take what I say with a helping of salt @thestryker

You're spot on with how it works. It's just the nodes have all sorts of different properties that limit bounds.

TSMC's high density libraries have been so far ahead of everyone else that it makes going with anyone else for high performance chips that are power limited a non-starter. High performance on the other hand hasn't been anywhere near as far ahead. I would love to know where Samsung's nodes realistically fall here, but with how they've been struggling there aren't many products to see real world reflections.