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Big Tech Players Start To Adopt The RISC-V Chip Architecture

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AgentLozen

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I've never heard of RISC-V before this article. It sounds like an interesting technological development.

I wonder how the RISC-V ISA compares to ARM's ISA.

I wouldn't mind paying for the implementation of this ISA as a CPU or micro controller, but it's nice to know that you can develop for something like this without proprietary restrictions.

I like to think about a utopian future 50 years from now where free and efficient technologies like this reign supreme. What I want to hear is, "Today is better than yesterday". What we seem to get, unfortunately, is, "We're worse off than yesterday."
 

peter.kese

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Agentlozen, apparently RISCV instruction set allows one to build even simpler processors than ARM. I've read someplace that a very simple 64bit ISCV CPU core (without caches) can be made of approx 50% less transistors than a comparable ARM v8.
 

AgentLozen

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Gosh. That's really cool. Like I said earlier, I've only hard o this ISA today so I'm not well informed about it. Do you remember where that statistic came from?
 

AgentLozen

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On one hand the article reads,


An ISA that's supposed to compete with x86 and ARM could belong to a CPU. I don't think x86 is used in simple micro contollers.

However,



It's apparently being backed by Nvidia, IBM, and AMD. Each of these companies has it's own instruction set it develops already and I don't seem them building new flagship CPUs around RISC-V any time soon. In this case, RISC-V seems like it's more suited to integrated into a small, simple device.

At any rate, I plan to keep an eye on it in the future.

edit: changed wording for clarity
 

bit_user

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Since then, chip companies such as AMD, Qualcomm, and IBM have also joined the members list.
I wonder how hard it'd be to take something like Ryzen and replace the instruction decoder + adjust the register file to adapt it for RISC-V. It might not be quite as efficient as if they made a purpose-built RISC-V chip, but it'd certainly be one of the faster implementations on the market.
 

bit_user

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AMD has already made an ARM chip (8-core A57), so I think they're open minded and not necessarily wed to x86.

Nvidia has so far used RISC-V to replace the proprietary microcontroller integrated into their GPUs. I'm not aware of any plans for it to replace ARM in their Tegra SoC, but I think they'd probably prefer not to pay royalties to ARM if they could avoid it.
 

bit_user

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One problem with ARMv8-A is that it requires backward-compatibility with ARMv7-A. They also have multiple instruction encoding formats. So, ARM has accumulated a bit of legacy, just like x86.

ARMv8-A also requires things like NEON 128-bit SIMD support. That actually highlights one potential down-side of a completely open ISA, which is that you could start to have implementations appearing with different, incompatible extensions. ARM is very strict about which instructions all implementations must support. I'm sure the RISC-V foundation is aware of this hazard, and it'll be interesting to see how they manage it.

RISC-V gets a clean sheet design, allowing its instruction decoder to be simpler. Over time, the cruft will probably build up, but certain embedded applications might not need to provide binary compatibility with earlier generations.

Now, ARM has a different family of ISAs that's targeted specifically at microcontrollers. I don't know as much about it, but if we're talking about that market, then it should be the basis for comparison:

https://en.wikipedia.org/wiki/ARM_Cortex-M
 

bit_user

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He also added that the company will build a ... 4,096-core "ET-Minion" energy-efficient chip, with each core having its own floating point unit.
If these are all independent, single-threaded cores, that's just silly. The reason GPUs use wide SIMD is to economize on instruction decoding and data routing logic. Not to mention hardware thread scheduling and huge savings from having only one MMU.
 

davidpatterson

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Below is a few paragraphs about RISC-V, but you can learn more at riscv.org:

"The renewed need in the post-PC
era for simpler ISAs led to the RISC-V.
(This is pronounced “RISC five” since
it the fifth RISC architecture from UC
Berkeley.) Keeping with its heritage,
the RISC-V is a minimalist ISA; in fact,
the base ISA is remarkably similar to
its great-great-grandparent RISC-I.
One indication of complexity is the
size of the documentation. The ISA
manual for x86-32 is 2,198 pages or
2,186,259 words. The RISC-V equivalents
are 236 pages or 76,702 words.
If someone were to read manuals as
an (incredibly boring) full-time job—
eight hours a day for five days a week—
it would take a month to read the x86-
32 manual but less than a day to read
the RISC-V manual.
Because it’s new, the RISC-V avoids
the mistakes of past ISAs.
For example, it’s modular: a small base ISA runs a full
software stack (OS, libraries, debuggers,
and compilers). The base is frozen and
will never change, giving programmers
a stable target. The modularity comes
from optional standard extensions:
multiply and divide, floating-point
arithmetic, atomic operations, compact
code, and vector instructions.
To achieve the software-desirable
goal of a single ISA that works from
the smallest to the largest computers,
it needs to lead to efficient designs for
both edge devices and the cloud. To
empower large-scale computers, the
RISC-V offers 64-bit as well as 32-bit
address versions. Minimalism and
modularity enable small and lowenergy
implementations of the RISC-V,
which helps embedded applications.
While some argue that ISA complexity
doesn’t matter for high-end processors,
it does matter for low-cost
applications, which the lack of success
of the 80x86 illustrates. A universal
ISA must work well everywhere. To
support domain-specific architectures
(DSAs), such as Google’s tensor
processing unit (TPU), the RISC-V
reserves opcode space to allow tight
coupling of custom accelerators.
However, the RISC-V’s most unconventional
feature is that it’s open. Its
future is free from the fate or decisions
of a single corporation, which have
doomed numerous ISAs in the past.8
Instead, it belongs to a nonprofit foundation
with more than 75 corporate
members (riscv.org). Its goal is to maintain
the stability of the RISC-V; evolve
the ISA slowly and carefully, keeping
technological changes in mind; and to
try to make it as popular as software
open source projects like Linux. This
openness enables any organization to
develop and share implementations of
the RISC-V. Competition, a free market,
and open implementations might
lower costs and increase innovation,
similar to the benefits of open source
software. Open designs also reduce
the odds of unwanted malicious secrets
being hidden in a processor."
 
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