Brisbane Latency 14 Cycles

Parrot

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Anandtech have posted a correction to their article:
Updated - 1/5/07: Although AMD previously did not mention any issues with our findings, we were contacted today and informed that the latency information both ScienceMark and CPU-Z produced is incorrect. The Brisbane core's L2 latency should be 14 cycles, up from 12 cycles and not 20 cycles.
LINK
 

evilr00t

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Anandtech have posted a correction to their article:
Updated - 1/5/07: Although AMD previously did not mention any issues with our findings, we were contacted today and informed that the latency information both ScienceMark and CPU-Z produced is incorrect. The Brisbane core's L2 latency should be 14 cycles, up from 12 cycles and not 20 cycles.
LINK

Cool, thanks.
 

1Tanker

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This is a good post and good follow up ---- this makes much more sense for a straight up die shrink -- from the cache perspective.
While it's good if the cache latency truly isn't that much higher, it sort of dampens any hope of them having done this in preperation for more L2 or L3. :wink:
 

Barcelona_Xtreme

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This is a good post and good follow up ---- this makes much more sense for a straight up die shrink -- from the cache perspective.
While it's good if the cache latency truly isn't that much higher, it sort of dampens any hope of them having done this in preperation for more L2 or L3. :wink:

Indeed, they will be adding more cache to their upcoming line of processors.
My guess on this is that K8L with 4 cores on the same die could have a more complex cache coherence problem to resolve since it has 4 L2 caches and one L3 cache to sync. A 2-cycle delay seems reasonable to compensate this increase of complexity. Another speculation though, seems that AMD's plan to test some changes of L2 cache layout before they go into K8L. This is just speculation
 

qcmadness

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Indeed, they will be adding more cache to their upcoming line of processors.
My guess on this is that K8L with 4 cores on the same die could have a more complex cache coherence problem to resolve since it has 4 L2 caches and one L3 cache to sync. A 2-cycle delay seems reasonable to compensate this increase of complexity. Another speculation though, seems that AMD's plan to test some changes of L2 cache layout before they go into K8L. This is just speculation
It does not make much sense as AMD stated that the Windsor=>Brisbane transition is a simple die shrink.
 

qurious69ss

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Spinning is the name of the game. Most people don't care about cache latency and a 3-7% performance loss is very negligible to the average user who will never see the difference, yet a die shrink and more importantly a PR key point is worth a lot of money so who cares if the fact come out later. Answer: NOBODY. It's all about the money. Yesterday they say that it was for future upgrade, today they say that the software is at fault, tomorrow they will say who cares, it is all a big game and we are all just pawns.
 

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