News Broadcom unveils gigantic 3.5D XDSiP platform for AI XPUs — 6000mm² of stacked silicon with 12 HBM modules

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Didn't AMD use face-to-face stacking for X3D? If the "Cost-Efficient Node" shown in their diagrams is something like TSMC N6, this makes me wonder whether they could also just put the L3 cache in the base tile.
 
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