News Broadcom unveils gigantic 3.5D XDSiP platform for AI XPUs — 6000mm² of stacked silicon with 12 HBM modules

[Admin]

Broadcom's 3.5D XDSiP platform for high-performance processors uses TSMC's CoWoS and other packaging technologies to build a system-in-packages comprising 6000mm² of 3D-stacked silicon with 12 HBM modules.

Broadcom unveils gigantic 3.5D XDSiP platform for AI XPUs — 6000mm² of stacked silicon with 12 HBM modules : Read more

 

[bit_user]

Didn't AMD use face-to-face stacking for X3D? If the "Cost-Efficient Node" shown in their diagrams is something like TSMC N6, this makes me wonder whether they could also just put the L3 cache in the base tile.