The 5060 ti 8 GB has a bus width of 128 bits, and the 5060 ti 16 GB has the same bus width with twice the number of memory chips, so I'm curious how this works?I don't understand
Thank you very much. Just knowing that 2 GB is currently the largest capacity for GDDR7 memory, I thought that maybe the chips on the back of the board share the same bus, but I couldn't find confirmation of this.The simple explanation. More capacity, same bus. You can use larger chips, you can use a set of two chips per channel. Very similar to how dual channel memory works with 4 slots.
Each bus is 32bit, it can support 1 or 2 chips.
If I recall in a more technical manner there is an additional pin that is used to indicate stacked memory and is used to shift between address locations.
Well, that isn't exactly correct. 3GB chips do exist for GDDR7. Just hasn't been launched in a product yet. Nvidia 50 series Super cards are expected to have these. So 9GB, 12GB, 18GB, and 24GB variants of existing 6GB/8GB/12GB/16GB cards could happen. They probably won't do all of the possibilities though, as there is little call for a 24GB 5060Ti, and that would be doubly expensive.Thank you very much. Just knowing that 2 GB is currently the largest capacity for GDDR7 memory, I thought that maybe the chips on the back of the board share the same bus, but I couldn't find confirmation of this.
We need a 5050 with 6 GB VRAM and 64 bit bus width!Well, that isn't exactly correct. 3GB chips do exist for GDDR7. Just hasn't been launched in a product yet. Nvidia 50 series Super cards are expected to have these. So 9GB, 12GB, 18GB, and 24GB variants of existing 6GB/8GB/12GB/16GB cards could happen. They probably won't do all of the possibilities though, as there is little call for a 24GB 5060Ti, and that would be doubly expensive.
We need a 5050 with 6 GB VRAM and 64 bit bus width