Question can i make compile stage shorter in VCS (synopsys)?

[asifvg1]

if i changed few lines from a specific verilog of design and now i want to recompile, can i compile just the related files or i need to compile the whole design again?
im using VCS tool by synopsys.

 

[Ralston18]

Not really certain about your question. (Full disclosure.)

That said, what I would do both.

Recompile your "few lines" and if those lines pass or succeed then recompile the entire design.

Otherwise, I believe more information is needed...

 

[asifvg1]

i dont want to recompile the entire design, i made some changes in one file and im asking if i can shorten the compile stage somehow?
because i made change just in one file and recompiling the entire design seem to me like something i can avoid from.