If their 7nm node has only 33% the good dies of TSMC wafer to wafer, then their 5nm node is going to have a defect rate unheard of in the chip manufacturing world. But that’s about right using DUV to build feature sizes >= 10x smaller than the light wavelength used. The only technique they could use is quad patterning which introduces 3 additional exposures thus compounding defects by 3x. Also, having to produce an additional 3x masks is not cheap.
It’s interesting from a scientific standpoint that SMIC has been able to make 5nm class transistors without EUV, however TSMC, Samsung, Intel, and IBM did the same thing in the beginning stages of 7nm and 5nm R&D as EUV was not available yet, and they were simply trying to produce working transistors to validate their design work and knew it was not economical, so to push this costly and defect ridden process into wide scale production is “Austin Powers: I too like to live dangerously” territory lol.