Confusion on Calculating Memory Bandwidth? (In Bytes)

[turkey3_scratch]

So, if you have any DDR memory that is, say, 1600Mhz. The maximum theoretical bandwidth for that would be 12,800 MB/s. But I don't under stand why. Each clock two bits can be transferred between the I/O Bus and the memory controller, and with DDR4 16 bits per clock between the storage array and IO bus. So, if two bits can be transferred per cycle, and for DDR 1600Mhz memory the MC frequency is 800Mhz, would not the memory bandwidth be frequency * 2 ? Or in this case, 800 * 2 or 1600 Megabytes per second or 1.6Gbps? And then divide that by 8 to get GBps?

But that's not how it works. You take, for 1600Mhz memory, that * 8 which = 12,800 MB/s. And that is bytes. It doesn't make sense to me. How is the bandwidth * (64 / 8) calculation derived for memory, because it doesn't make sense if only two bits are transferred per clock cycle.

 

[Sakkura]

1600 MT/s x 64 bits / 8 bits/byte = 12800 MB/s

Every transfer is 64 bits, AKA 8 bytes. You know, 64-bit CPUs and all that. Not sure where you got the 2-bit thing from.

 

[turkey3_scratch]

Oh, I think I was misinterpreting this graph. I'm reading the Hardwaresecrets thing here. I thought that the two data chunks was two bits, though now I realized the word "chunk".

But there's another confusion I have. It reads:

however, the DDR chip transfers two bits between the memory array and the I/O buffer, so to match the I/O interface speed this datapath has to work at 200 MHz (200 MHz x 2 = 400 MHz).

So let's just talk about DDR3. In this case, 8 bits of data are transferred per cycle from the memory array to the I/O Buffer. If this is DDR3 1600Mhz we are talking about, the datapath from the array to buffer has to be 200Mhz. But that would be only 200Mhz * 8 bits per second or 200MBps when in fact the bandwidth of the DDR3-1600Mhz is 12800 MB/s, meaning it'd be slower?

 

[InvalidError]

The memory clock for DDR3-1600 is 800Mhz, the data transfer rate is 2x due to DDR, the memory controller data path width to the DIMM is 64bits wide, which yields 800MHz x 2 x 64bits = 102.4Gbps or 12.8GB/s.

It is not 8 bits of data transferred per transfer, it is 64bits... 8 bytes.

 

[turkey3_scratch]

The memory clock for DDR3-1600 is 800Mhz, the data transfer rate is 2x due to DDR, the memory controller data path width to the DIMM is 64bits wide, which yields 800MHz x 2 x 64bits = 102.4Gbps or 12.8GB/s.

It is not 8 bits of data transferred per transfer, it is 64bits... 8 bytes.

That makes sense.

But what about the frequency of the memory array to the I/O Bus? The difference in each DDR version is how many bits can be transferred per cycle each version. 16 for DDR4. Wouldn't that data transfer rate have to equal the memory controller to the DIMM's transfer rate?

 

[InvalidError]

The data transfer rate per cycle per pin is the same for all DDR: two bits. It is in the name: DOUBLE data rate, twice the clock frequency.

The width of the DDR interface for PC-style DDR1/2/3/4 DIMMs is 64bits, 72bits for ECC DIMMs. If you want to transfer more bits per DRAM clock cycle, you have to move up to Quad Data Rate.

You must be confused with something else, such as burst length or internal bank count.

 

[turkey3_scratch]

I'm talking about prefetch, as is talked about here http://www.hardwaresecrets.com/everything-you-need-to-know-about-ddr-ddr2-and-ddr3-memories/5/ . But now your mentioning of two bits per pin is confusing me more. DDR4 has 288 pins. Wouldn't it have 64 pins instead then?

 

[InvalidError]

The DIMM may have 200+ pins but out of those, there are ~30 control pins, a handful of Vccio, Vcore, Vref, etc. pins and 100+ grounds. Why do DIMMs have as many ground pins as everything else combined? Signal integrity reasons: to keep the multi-Gbps IO on modern chips and board-to-board interconnects working properly, they need tons of ground pins to keep signal lines tightly coupled to ground to minimize crosstalk, transmission line impedance issues, ground bounce, etc.

BTW, as for "prefetch", this is also called "burst transfer" and refers to the DRAM's ability to stream multiple words in a single read/write operation, it has absolutely nothing to do with the interface bandwidth itself. What it does do is enable the DRAM to make more efficient use of that bandwidth by pipelining memory commands between banks and ranks: while one memory bank is in the process of execuring a 8n read or write burst on one memory bank, the command lines can be used to setup the next memory access on a different bank to reduce dead time on the data bus between operations.

 

[turkey3_scratch]

Thank you very informative.