Scotteq
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Scotteq
Splendid
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Hmm.... how to answer in plain english.... without jargon... water seems an appropriate analogy...
You're thinking in one dimension: 1 pipe, 1 clock, 1 bit of data, 1 thing happens. But it doesn't work like that.
The first image i'd like to give you is that the system buss is more like a bunch of fire hoses, all transferring types of data from different places, all at the same time, and all of it aimed at the Processor. So, if at a given instant a particular pipe doesn't have any 'water' in it, then the processor simply grabs some from another pipe in the buss.
The second thing is that the system buss can/does transfer data more than once per clock cycle - Think of a wave: There's a peak, a valley, and a couple points in the front/center, and rear/center...
Now - You can think of the speed of the Buss as more like water pressure in the hose - how fast the pump is running. The flow of data is constant, what the speed does is control how fast it moves from point to point.
So the processor has a pretty big task: All of these pipes, all shooting data at it, all at the same time, multiple times per clock. It Needs to get the data in, calculated, and back out as fast as possible so it can move on to the next. So if the Processor can do 5 or 10 or 20 things in that clock cycle, then it can service a faster/wider buss (more/fatter pipes, under greater pressure)
You're thinking in one dimension: 1 pipe, 1 clock, 1 bit of data, 1 thing happens. But it doesn't work like that.
The first image i'd like to give you is that the system buss is more like a bunch of fire hoses, all transferring types of data from different places, all at the same time, and all of it aimed at the Processor. So, if at a given instant a particular pipe doesn't have any 'water' in it, then the processor simply grabs some from another pipe in the buss.
The second thing is that the system buss can/does transfer data more than once per clock cycle - Think of a wave: There's a peak, a valley, and a couple points in the front/center, and rear/center...
Now - You can think of the speed of the Buss as more like water pressure in the hose - how fast the pump is running. The flow of data is constant, what the speed does is control how fast it moves from point to point.
So the processor has a pretty big task: All of these pipes, all shooting data at it, all at the same time, multiple times per clock. It Needs to get the data in, calculated, and back out as fast as possible so it can move on to the next. So if the Processor can do 5 or 10 or 20 things in that clock cycle, then it can service a faster/wider buss (more/fatter pipes, under greater pressure)
- Apr 29, 2006
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Lol, not sure that was plain english. Something else to keep in mind, not all CPU activities require bus access. If the CPU has to do some heavy work, its not transferring anything through the bus. This is why the CPU has to run faster then the bus, as there are many times where the CPU has to work while the bus won't need to transfer any data.
Thank you; I hear what you are saying.
Followon question 1: how then do you determine when 'enough is enough' in terms of the difference between the RAM speed and the CPU speed?
Followon question 2: is RAM speed determined by Memory Bus speed and/or is RAM speed equal to Memory Bus speed?
Followon question 1: how then do you determine when 'enough is enough' in terms of the difference between the RAM speed and the CPU speed?
Followon question 2: is RAM speed determined by Memory Bus speed and/or is RAM speed equal to Memory Bus speed?
- Apr 29, 2006
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RAM speed or bus speed? "enough" depends on who you ask. I'm broke, so it usually depends on my budget. Others however have tons of money, and want nothing but the speed record. Our version of "enough" will be very different.
Yes? If I understand your question correctly, the ram speed is determined by the memory bus speed and because of that, its equal to it. The effective speed will be double the actual speed because its DDR ram. On older computers its a value related to the FSB, but all newer CPUs sold now (except for Via's) have the memory controller on the CPU itself, and has no relation to the other buses.
Question 1: I was asking about RAM speed. So are you saying there is NO logical limit on how much faster than RAM the CPU should be? I would have thought there was a point after which going further made no sense.
Question 2: OK so when we are talking about RAM speed we are really talking about Memory Bus speed?
Zenthar
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- Dec 31, 2007
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Question 1: Theoretically, I'm not sure there would be any gain of going "[CAS]/[RAM Speed] > 1/[Memory Bus Speed]". At that point the RAM would just be able to get data faster than the bus can send it to the CPU ... But technically yes, the faster the better, that is why the CPUs have built-in cache running at the same speed as the CPU.
Question 2: When we are talking about RAM speed, we are really talking about "2 x [Memory Bus Speed]" because it's DDR (Double Data Rate)
Question 2: When we are talking about RAM speed, we are really talking about "2 x [Memory Bus Speed]" because it's DDR (Double Data Rate)
Thanks.
Question 1: you lost me -- what is CAS?
Question 2: I get you, but that was not my main point. MAIN POINT: I do not think there's any benefit to having a RAM that can move data out any faster than twice the Memory Bus Speed. Am I correct about that?
CAS is the latency of the RAM, in RAM cycles. If RAM has a CAS latency of 7, it takes 7 cycles to access the data. If one RAM can run at 400Mhz with a CAS of 2, and one can run at 800Mhz with a CAS of 4, it'll take the same amount of time to access any given piece of data, however, the RAM operating at 800Mhz can send more data over an equal length of time (though it's likely not actually going to send double).
For question 2, it depends on some things. Firstly, DDR RAM actually sends data twice as fast as its actual speed. Hence Double Data Rate. Memory buses might also operate on a similar principle. To the best of my knowledge, Intel's FSB on socket 775 is quad-pumped--it sends four bits per Mhz. This is why your FSB in the BIOS usually will say 266, 333, or 400, while your processor might say 1066, 1333, or 1600. If the RAM speed and Memory Bus have the same EFFECTIVE speed, no, being able to move data out of RAM faster will do no good. This is why we usually match them 1:1, letting DDR2 800 RAM operate at ony 667Mhz if the FSB is 333Mhz/1333Mhz.
For question 2, it depends on some things. Firstly, DDR RAM actually sends data twice as fast as its actual speed. Hence Double Data Rate. Memory buses might also operate on a similar principle. To the best of my knowledge, Intel's FSB on socket 775 is quad-pumped--it sends four bits per Mhz. This is why your FSB in the BIOS usually will say 266, 333, or 400, while your processor might say 1066, 1333, or 1600. If the RAM speed and Memory Bus have the same EFFECTIVE speed, no, being able to move data out of RAM faster will do no good. This is why we usually match them 1:1, letting DDR2 800 RAM operate at ony 667Mhz if the FSB is 333Mhz/1333Mhz.
You seem to end up agreeing that there is no benefit in having an EFFECTIVE RAM speed higher than the EFFECTIVE speed of the Memory Bus. The control here, from the standpoint of the CPU, seems to be the speed of the Memory Bus and not of the RAM where the effective speed of the RAM is higher and the RAM speed where the effective speed of the Memory Bus is higher. Right?
My comments were bolixed-up just above.
My comments after your first paragraph were:
I think you are saying the EFFECTIVE speeds of the 400 RAM and the 800 RAM here are the same. If so, wouldn't they by definition be sending THE SAME amount of data over the same length of time?
My comments after your second paragraph were:
You seem to end up agreeing that there is no benefit in having an EFFECTIVE RAM speed higher than the EFFECTIVE speed of the Memory Bus. The control here, from the standpoint of the CPU, seems to be the speed of the Memory Bus and not of the RAM where the effective speed of the RAM is higher and the RAM speed where the effective speed of the Memory Bus is higher. Right?
My comments after your first paragraph were:
I think you are saying the EFFECTIVE speeds of the 400 RAM and the 800 RAM here are the same. If so, wouldn't they by definition be sending THE SAME amount of data over the same length of time?
My comments after your second paragraph were:
You seem to end up agreeing that there is no benefit in having an EFFECTIVE RAM speed higher than the EFFECTIVE speed of the Memory Bus. The control here, from the standpoint of the CPU, seems to be the speed of the Memory Bus and not of the RAM where the effective speed of the RAM is higher and the RAM speed where the effective speed of the Memory Bus is higher. Right?
Scotteq
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Robby - The difference is measurable with benchmarking tool, but as a practical matter (meaning - in terms of user application) there is little/no noticable difference.
On the front page, go to the memory section. There are a couple recent articles where this was tested.
On the front page, go to the memory section. There are a couple recent articles where this was tested.
Upendra09
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- Mar 4, 2009
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Going back to the first question. having an FSB faster than the CPU is like shoving food into someones mouth faster than they can chew and swallow, resulting in gross puke, or for a computer, failure to start up and LOTS of crashes.
followon question 1: You actually don't want a lot of difference, like you don't want to have memory take a long time to get data and give it to the cpu, but you don't want the memory to be faster than the CPU can think either. They have a ratio of CPU to RAM 1:1 is the best. 800 FSB to 800 mhz RAM equals good teamwork and fast computer.
follow on question 2: I think RAM speed is memory bus speed, that is why 800 RAM can be downclocked to 667, 533, etc.
As for CAS it is just the latency, faster speed like 800, 1066, or 1333, doesn't mean less latency, just means faster memory bus.
I think this makes all further questions void.
I hope i didn't just complicate everything, instead of making it clear
hope it helps
I haven't reviewed every comment above, and
some of the ones I have reviewed don't appear
to provide clear answers to the original question.
From what I do understand of the original question,
it's important to appreciate that a modern CPU has
multiple levels of internal hardware cache, e.g.
Level 1 cache, Level 2 cache, and so on.
Many basic instructions of a CPU do NOT require
that it communicate anything to or from RAM.
A simple example is the assembly instructions A1A --
add 1 to the A register, or CLA -- zero the A register.
Similarly, if a program instruction has already
been fetched from RAM, the CPU will store it
in a local high-speed area called a cache,
to render that instruction more quickly
accessible the next time it is needed.
These internal caches eliminate the need
for the CPU to access RAM over the "bus"
that connects the CPU with RAM.
A "bus" is very much like a group of
many parallel wires, just like the
older 40-pin ribbon cables.
So, you can see how a CPU actually cycles
many many times, on average, before it
actually needs to send or receive data
to or from Random Access Memory ("RAM"),
or further on down the chipset to the
Southbridge, which connects the CPU
to relatively slow peripherals, like disk drives.
Now, as one comment correctly explained above,
Intel CPUs are "quad-pumped". This means that
they transmit and receive data over the Front Side Bus
FOUR TIMES for every tick of that FSB clock.
The FSB is the set of parallel wires that connect
the CPU with the Northbridge, where the memory
controller is typically located. In the Intel Core i7
architecture, the memory controller has been
moved into the CPU itself.
Thus, if the raw FSB clock is ticking at 400 MHz,
the Intel CPU wired to that FSB will send data
4 TIMES as fast, or 400 x 4 = 1600 MHz.
With Intel chipsets that use a Northbridge,
there is a completely separate "bus" which
connects that Northbridge to RAM;
that other bus oscillates at its own
clock rate, which may or may NOT
be the same as the FSB raw clock rate.
When the FSB and DRAM buses oscillate
at the same rate, that is generally called
"synchronous" or a 1 : 1 FSB : DRAM ratio.
A typical 1 : 1 ratio sets the raw FSB clock at 400 MHz
and the DRAM clock at 400 MHz. This produces an
effective FSB rate of 1,600 MHz and an
effective DRAM rate of 800 MHz aka PC2-6400 (or PC3-6400).
The CPU-Z program will tell you what your
FSB : DRAM ratio is for any given system
configuration.
I hope this helps.
MRFS
some of the ones I have reviewed don't appear
to provide clear answers to the original question.
From what I do understand of the original question,
it's important to appreciate that a modern CPU has
multiple levels of internal hardware cache, e.g.
Level 1 cache, Level 2 cache, and so on.
Many basic instructions of a CPU do NOT require
that it communicate anything to or from RAM.
A simple example is the assembly instructions A1A --
add 1 to the A register, or CLA -- zero the A register.
Similarly, if a program instruction has already
been fetched from RAM, the CPU will store it
in a local high-speed area called a cache,
to render that instruction more quickly
accessible the next time it is needed.
These internal caches eliminate the need
for the CPU to access RAM over the "bus"
that connects the CPU with RAM.
A "bus" is very much like a group of
many parallel wires, just like the
older 40-pin ribbon cables.
So, you can see how a CPU actually cycles
many many times, on average, before it
actually needs to send or receive data
to or from Random Access Memory ("RAM"),
or further on down the chipset to the
Southbridge, which connects the CPU
to relatively slow peripherals, like disk drives.
Now, as one comment correctly explained above,
Intel CPUs are "quad-pumped". This means that
they transmit and receive data over the Front Side Bus
FOUR TIMES for every tick of that FSB clock.
The FSB is the set of parallel wires that connect
the CPU with the Northbridge, where the memory
controller is typically located. In the Intel Core i7
architecture, the memory controller has been
moved into the CPU itself.
Thus, if the raw FSB clock is ticking at 400 MHz,
the Intel CPU wired to that FSB will send data
4 TIMES as fast, or 400 x 4 = 1600 MHz.
With Intel chipsets that use a Northbridge,
there is a completely separate "bus" which
connects that Northbridge to RAM;
that other bus oscillates at its own
clock rate, which may or may NOT
be the same as the FSB raw clock rate.
When the FSB and DRAM buses oscillate
at the same rate, that is generally called
"synchronous" or a 1 : 1 FSB : DRAM ratio.
A typical 1 : 1 ratio sets the raw FSB clock at 400 MHz
and the DRAM clock at 400 MHz. This produces an
effective FSB rate of 1,600 MHz and an
effective DRAM rate of 800 MHz aka PC2-6400 (or PC3-6400).
The CPU-Z program will tell you what your
FSB : DRAM ratio is for any given system
configuration.
I hope this helps.
MRFS
Upendra09
Distinguished
- Mar 4, 2009
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