I haven't reviewed every comment above, and
some of the ones I have reviewed don't appear
to provide clear answers to the original question.
From what I do understand of the original question,
it's important to appreciate that a modern CPU has
multiple levels of internal hardware cache, e.g.
Level 1 cache, Level 2 cache, and so on.
Many basic instructions of a CPU do NOT require
that it communicate anything to or from RAM.
A simple example is the assembly instructions A1A --
add 1 to the A register, or CLA -- zero the A register.
Similarly, if a program instruction has already
been fetched from RAM, the CPU will store it
in a local high-speed area called a cache,
to render that instruction more quickly
accessible the next time it is needed.
These internal caches eliminate the need
for the CPU to access RAM over the "bus"
that connects the CPU with RAM.
A "bus" is very much like a group of
many parallel wires, just like the
older 40-pin ribbon cables.
So, you can see how a CPU actually cycles
many many times, on average, before it
actually needs to send or receive data
to or from Random Access Memory ("RAM"),
or further on down the chipset to the
Southbridge, which connects the CPU
to relatively slow peripherals, like disk drives.
Now, as one comment correctly explained above,
Intel CPUs are "quad-pumped". This means that
they transmit and receive data over the Front Side Bus
FOUR TIMES for every tick of that FSB clock.
The FSB is the set of parallel wires that connect
the CPU with the Northbridge, where the memory
controller is typically located. In the Intel Core i7
architecture, the memory controller has been
moved into the CPU itself.
Thus, if the raw FSB clock is ticking at 400 MHz,
the Intel CPU wired to that FSB will send data
4 TIMES as fast, or 400 x 4 = 1600 MHz.
With Intel chipsets that use a Northbridge,
there is a completely separate "bus" which
connects that Northbridge to RAM;
that other bus oscillates at its own
clock rate, which may or may NOT
be the same as the FSB raw clock rate.
When the FSB and DRAM buses oscillate
at the same rate, that is generally called
"synchronous" or a 1 : 1 FSB : DRAM ratio.
A typical 1 : 1 ratio sets the raw FSB clock at 400 MHz
and the DRAM clock at 400 MHz. This produces an
effective FSB rate of 1,600 MHz and an
effective DRAM rate of 800 MHz aka PC2-6400 (or PC3-6400).
The CPU-Z program will tell you what your
FSB : DRAM ratio is for any given system
configuration.
I hope this helps.
MRFS