Thought I had this figured out when I built my last PC but now I have questions.
It seems current Intel CPUs have 20 PCIe lanes. For example, for the i5-12400 Intel states 20 PCIe lanes and 8 DMI lanes. Since they’re listed separately I presume the DMI lanes are not part of the 20 PCIe lanes.
ark.intel.com
This shows 16 PCIe lanes for the GPU, 4 PCIe lanes for video, and 8 DMI lanes.
www.servethehome.com
But here it says “the CPU typically controls one PCIe slot and one M.2”.
That means 16 GPU +4 Video +4 M.2 = 24 lanes which means someone is getting shorted. How are the 20 lanes really allocated?
silentpc.com
The chart in the above link shows that some chipsets use 4 DMI lanes & some use 8 DMI lanes. What happens if you use a CPU with 8 DMI lanes & a chipset mobo with 4 DMI lanes? Or vice versa? Is the bandwidth cut in half in those scenarios?
It seems current Intel CPUs have 20 PCIe lanes. For example, for the i5-12400 Intel states 20 PCIe lanes and 8 DMI lanes. Since they’re listed separately I presume the DMI lanes are not part of the 20 PCIe lanes.
![ark.intel.com](/proxy.php?image=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fdam%2Fwww%2Fcentral-libraries%2Fxl%2Fes%2Fimages%2F2022-06%2Fkm-1920x1080-i5.png&hash=31c02cab372fdc5371b1f85607ba07ce&return_error=1)
Intel® Core™ i5-12400 Processor (18M Cache, up to 4.40 GHz) Product Specifications
Intel® Core™ i5-12400 Processor (18M Cache, up to 4.40 GHz) quick reference guide including specifications, features, pricing, compatibility, design documentation, ordering codes, spec codes and more.
![ark.intel.com](/proxy.php?image=https%3A%2F%2Fark.intel.com%2Fetc.clientlibs%2Fsettings%2Fwcm%2Fdesigns%2Fintel%2Fdefault%2Fresources%2Ffavicon-32x32.png&hash=221024e78cd0d7340a5fc6395a18d5b6&return_error=1)
This shows 16 PCIe lanes for the GPU, 4 PCIe lanes for video, and 8 DMI lanes.
Intel Z690 Chipset Block Diagram - ServeTheHome
Intel Z690 Chipset Block Diagram
But here it says “the CPU typically controls one PCIe slot and one M.2”.
That means 16 GPU +4 Video +4 M.2 = 24 lanes which means someone is getting shorted. How are the 20 lanes really allocated?
Bottlenecks
Computer speed has always been an elusive target. Numerous components work together to create a seamless computer experience. If one of those components is dragging behind the other components, this creates a bottleneck
The chart in the above link shows that some chipsets use 4 DMI lanes & some use 8 DMI lanes. What happens if you use a CPU with 8 DMI lanes & a chipset mobo with 4 DMI lanes? Or vice versa? Is the bandwidth cut in half in those scenarios?