CPU-Z Cache 16 way explanation

[Devonn]

Hello,

Just studying, having trouble understanding what is meant in the CPU-Z Cache section. I can understand that, say the L1 cache is 8-way on a 4 core CPU because of hyperthreading, but I dont understand why a L3 cache would be 16 way.

My Athlon II x4 620 at home claims to have only a 2-way 'set associative' for the L1 data and L1 inst. and a 16 way for the L2 Cache.

Can someone explain simply how it is reaching the conclusion of 16 way, when I have 4 cores and 4 threads, in the L2 cache? Or how a L3 cache would be 16 way with 4 cores and 8 threads?

 

[DonkeyOatie]

It's just a way of organizing the L2 cache. I don't really understand the question.


For n-Way Set Associative Cache the memory cache is divided in several blocks (sets) containing “n” lines each. So on a 4-way set associative cache the memory cache will have 2,048 blocks containing four lines each (8,192 lines / 4), on a 2-way set associative cache the memory cache will have 4,096 blocks containing 2 lines each and on a 16-way set associative cache the memory cache will have 512 blocks containing 16 lines each. Depending on the CPU the number of blocks will be different, of course.

Read more at http://www.hardwaresecrets.com/how-the-cache-memory-works/8/#uGjsmJfzRmxR2GVx.99