Trfc: Refresh Cycle Time. The minimum amount of time that must exist between an Auto-Refresh command and the first Row-Active or Auto-Refresh command issued to a bank on a DRAM IC. Trfc is very density-dependent. Since Trefi is constant at 7.8 microseconds and the retention time is constant at 64 milliseconds high density DRAM chips must refresh multiple rows during each auto-refresh cycle. This is performed by using multiple subarrays inside of each memory array and refreshing one row per subarray during each auto-refresh cycle. Higher density chips are still subject to the...
Trfc: Refresh Cycle Time. The minimum amount of time that must exist between an Auto-Refresh command and the first Row-Active or Auto-Refresh command issued to a bank on a DRAM IC. Trfc is very density-dependent. Since Trefi is constant at 7.8 microseconds and the retention time is constant at 64 milliseconds high density DRAM chips must refresh multiple rows during each auto-refresh cycle. This is performed by using multiple subarrays inside of each memory array and refreshing one row per subarray during each auto-refresh cycle. Higher density chips are still subject to the same current draw limits as smaller density chips, so refreshing higher density chips takes longer because a greater number of subarrays need to be refreshed using the same amount of current.