DDR2-667 and DDR3-1333 bandwidths with 333MHz FSB

[sg84]

Taking as an example the QX9650 CPU, which has effective FSB of 1333MT/s which I assume to be 333MHz real FSB since its quad pumped, means that matched RAM would be DDR2-667 (bus clock of 333MHz, giving DRAM:FSB of 1:1) or DDR3-1333 (bus clock of 667MHzgiving DRAM:FSB of 2:1)

Now looking at the article on wiki for the QX9650 and memory matching,
http://en.wikipedia.org/wiki/Core_2#Synchronous_memory_modules

the one thing I cannot understand is why the DDR3-1333 would have a bandwidth of 10.67 GB/s in single channel mode, because I would assume, since the CPU FSB is 333MHz, the DDR3 memory is accessed 333 times a second, and in single channel 64-bit transfer mode would give 333x2x8=5.3GB/s (x2 because data transferred on rising and falling edges of clock pulse)

my basic understanding must be wrong so I'd like to know what really happens

 

[Zenthar]

You said it yourself: "bus clock of 667MHz". Therefore the calculation would be "667x2x8=~10.6GB/s", no?

Maybe there is something I didn't understand in your non-understanding .

 

[sg84]

i think what i cant understand is how the DDR bus clock can operate at 667MHz while the FSB is only at 333MHz

After some thinking, I have drawn how I think it works, since the CPU FSB is quad pumped and can accept data 4 times per clock cycle. The DDR works at 667MHz but is only double pumped and so the points when it can transfer coincide with the points where the FSB clock cycle can accept. The green curve is the CPU FSB with the blue dots the points where it can access. The black curve is the RAM bus clock, and the brown points are when it can transfer.

Please tell me if I have got it right or not.

 

[portal]

+1 for use of sin graph

 

[Zenthar]

First of all, I am no computer or electrical engineer so my understanding of the concepts might be highly flawd.

Just to let you know that conceptually you are right, the "quad-pump" FSB does "read/write" 4 times per cycle, but not exactly where you put them, it cannot read at top and bottom of the signal. To achieve that, they added a second signal with a 90 degree offset (trigonometrically speaking) so the more technicaly right graph would look like that:


There are 2 things to consider here■Marketing math: it's not because there is no-one to read the data that the RAM cannot transfer that much;
■RAM and FSB can run "asynchronously" (that is why you can get RAM to FSB ratio of 6:5 and things like that);
■There is a memory controller (MC) between the RAM and CPU (either on-die or not).

The CPU can access the MC at FSB speed and the MC can access RAM at memory bus speed. If both the memory bus and FSB bus run synchronously (round ratios like 1:1, 2:1, 1:2, ...), the memory content pretty much goes straight-through the controller to the CPU. If running asynchronously, the controller will "hold" (in some kind of internal memory, registry, cache) the data until the next FSB access gets the data; if you miss the bus (no pun intended), you got to wait for the next one.

Does this clarify things a bit for you?

 

[WazzaUK]

further reading:

http://www.directron.com/fsbguide.html
http://download.micron.com/pdf/technotes/ddr2/TN4706.pdf
http://www.intel.com/technology/memory/index.htm
http://en.wikipedia.org/wiki/DDR2_SDRAM
http://en.wikipedia.org/wiki/Memory_Divider
http://www.tomshardware.co.uk/ddr3-1333-shootout,review-29939-17.html

 

[sg84]

yeah i think i understand it now, thanks
although your sine wave drawing shows the memory curve having half the frequency of the FSB. I assume you meant it to be double?