Stringtheory :
I would have thought that RAM in separate banks would be relatively isolated from each other, so I'm surprised to hear any of this.
CPUs apply the same clock frequency and the same set of timings to all channels. If the channels' properties are different due to having different DIMM loadout, then it may mess up timings and IO driver properties which may get adjusted based on timings and frequency.
I haven't read Intel's DRAM controller specs but on FPGAs, IO blocks have many properties that can be either trained, pre-programmed or adjusted dynamically on a per-pin or per-group basis to cope with signal integrity issues. DDR3/4 chips also have a bunch of registers to tweak on-chip termination, delay-locked loops and other details. Mixing DIMMs makes things more complicated than they already are.
In the earlier days of the DDR4 draft spec, JEDEC didn't even officially support having more than one DIMM per channel due to signal integrity concerns and when it got put in, initial support was only up to 2133MT/s.